ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 625
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 625 of 826
- Download datasheet (20Mb)
• OVERFIE: Overflow Interrupt Enable
Set by software (by setting the OVERFIES bit) to enable the Overflow interrupt (OVERFIE).
Clear by software (by setting the OVERFIEC bit) to disable the Overflow interrupt (OVERFIE).
• RXSTALLDE: Received STALLed Interrupt Enable
Set by software (by setting the RXSTALLDES bit) to enable the Received STALLed interrupt (RXSTALLDE).
Clear by software (by setting the RXSTALLDEC bit) to disable the Received STALLed interrupt (RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
Set by software (by setting the CRCERRES bit) to enable the CRC Error interrupt (CRCERRE).
Clear by software (by setting the CRCERREC bit) to disable the CRC Error interrupt (CRCERRE).
• SHORTPACKETIE: Short Packet Interrupt Enable
Set by software (by setting the SHORTPACKETES bit) to enable the Short Packet interrupt (SHORTPACKETIE).
Clear by software (by setting the SHORTPACKETEC bit) to disable the Short Packet interrupt (SHORTPACKETE).
• NBUSYBKE: Number of Busy Banks Interrupt Enable
Set by software (by setting the NBUSYBKES bit) to enable the Number of Busy Banks interrupt (NBUSYBKE).
Clear by software (by setting the NBUSYBKEC bit) to disable the Number of Busy Banks interrupt (NBUSYBKE).
• FIFOCON: FIFO Control
For OUT and SETUP Pipe :
Set by hardware when the current bank is free, at the same time than TXOUTI or TXSTPI.
Clear by software (by setting the FIFOCONC bit) to send the FIFO data and to switch the bank.
For IN Pipe:
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See EPDISHDMA (UECONX register).
• PFREEZE: Pipe Freeze
Set by software (by setting the PFREEZES bit) to Freeze the Pipe requests generation.
Clear by software (by setting the PFREEZEC bit) to enable the Pipe request generation.
This bit is set by hardware when:
- the pipe is not configured
- a STALL handshake has been received on this Pipe
- An error occurs on the Pipe (PERR = 1)
- (INRQ+1) In requests have been processed
This bit is set at 1 by hardware after a Pipe reset or a Pipe enable.
• RSTDT: Reset Data Toggle
Set by software (by setting the RSTDTS bit) to reset the Data Toggle to its initial value for the current Pipe.
Cleared by hardware when proceed.
32058J–AVR32–04/11
Set by hardware when a new IN message is stored in the current bank, at the same time than RXINI.
Clear by software (by setting the FIFOCONC bit) to free the current bank and to switch to the next bank.
AT32UC3A
625
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