ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 172
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 172 of 826
- Download datasheet (20Mb)
22.4.2
22.4.3
22.4.4
22.4.5
22.4.6
32058J–AVR32–04/11
I/O Line or Peripheral Function Selection
Peripheral Selection
Output Control
Open Drain Mode
Inputs
When a pin is multiplexed with one or more peripheral functions, the selection is controlled with
the register GPER. If a bit in the register is set, the corresponding pin is controlled by the GPIO.
If a bit is cleared, the corresponding pin is controlled by a peripheral function.
The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection
is performed by accessing PMR0 (Peripheral Mux Register 0) and PMR1 (Peripheral Mux Regis-
ter 1).
When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is at 0,
the drive of the I/O line is controlled by the peripheral. The peripheral, depending on the value in
PMR0 and PMR1, determines whether the pin is driven or not.
When the I/O line is controlled by the GPIO, the value of ODER (Output Driver Enable Register)
determines if the pin is driven or not. When a bit in this register is at 1, the corresponding I/O line
is driven by the GPIO. When the bit is at 0, the GPIO does not drive the line.
The level driven on an I/O line can be determined by writing OVR (Output Value Register).
Each I/O line can be independently programmed to operate in open drain mode. This feature
permits several drivers to be connected on the I/O line. The drivers should only actively drive the
line low. An external pull-up resistor (or enabling the internal one) is generally required to guar-
antee a high level on the line when no driver is active.
The Open Drain feature is controlled by ODMER (Open Drain Mode Enable Register). The Open
Drain mode can be selected whether the I/O line is controlled by the GPIO or assigned to a
peripheral function.
The level on each I/O line can be read through PVR (Pin Value Register). This register indicates
the level of the I/O lines regardless of whether the lines are driven by the GPIO or by an external
component. Note that due to power saving measures, PVR register can only be read when
GPER is set for the corresponding pin or if interrupt is enabled for the pin.
Output Line Timings
The figure below shows the timing of the I/O line when setting and clearing the Output Value
Register by accessing OVR. The same timing applies when performing a ‘set’ or ‘clear’ access
i.e. writing to OVRS or OVRC. The timing of PVR (Pin Value Register) is also shown.
AT32UC3A
172
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