ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 280
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 280 of 826
- Download datasheet (20Mb)
25.9.4
Name:
Access Type:
Offset:
Reset value:
• FSLENHI: Receive Frame Sync Length High part
The four MSB of the FSLEN bitfield.
• FSEDGE: Frame Sync Edge Detection
Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register.
• FSOS: Receive Frame Sync Output Selection
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive
Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also deter-
mines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. Note: The four most
significant bits fo this bitfield are in the FSLENHI bitfield.
Pulse length is equal to ({FSLENHI,FSLEN} + 1) Receive Clock periods. Thus, if {FSLENHI,FSLEN} is 0, the Receive
Frame Sync signal is generated during one Receive Clock period.
• DATNB: Data Number per Frame
32058J-AVR32-04/11
MSBF
0x6-0x7
31
23
15
FSOS
–
–
7
0x0
0x1
0x2
0x3
0x4
0x5
FSEDGE
Receive Frame Mode Register
0x0
0x1
Selected Receive Frame Sync Signal
None
Negative Pulse
Positive Pulse
Driven Low during data transfer
Driven High during data transfer
Toggling at each start of data transfer
Reserved
30
22
14
RFMR
Read/Write
0x14
0x00000000
–
6
–
Frame Sync Edge Detection
Positive Edge Detection
Negative Edge Detection
FSLENHI
FSOS
LOOP
29
21
13
–
5
28
20
12
–
4
27
19
11
–
3
DATLEN
26
18
10
–
2
FSLEN
DATNB
RX_FRAME_SYNC Pin
25
17
–
9
1
AT32UC3A
Undefined
Input-only
Output
Output
Output
Output
Output
FSEDGE
24
16
8
0
280
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