ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 153
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 153 of 826
- Download datasheet (20Mb)
21. Peripheral DMA Controller (PDCA)
21.1
21.2
32058J–AVR32–04/11
Features
Overview
rev: 1.0.0.0
•
•
The Peripheral DMA controller (PDCA) transfers data between on-chip peripheral modules such
as USART, SPI, SSC and on- and off-chip memories. Using the PDCA avoids CPU intervention
for data transfers, improving the performance of the microcontroller. The PDCA can transfer
data from memory to a peripheral or from a peripheral to memory.
The PDCA consists of a number of DMA channels. Each channel has:
The PDCA communicates with the peripheral modules over a number of handshake interfaces.
The peripheral signals to the PDCA when it is ready to receive or transmit data. The PDCA
acknowledges the request when the transmission has started.
The number of handshake-interfaces may be higher than the number of DMA channels. If this is
the case, the DMA channel must be programmed to use the desired interface.
When a transmit buffer is empty or a receive buffer is full, an interrupt request can be signalled.
• A 32-bit memory pointer
• A 16-bit transfer counter
• A 32-bit memory pointer reload value
• A 16-bit transfer counter reload value
Generates Transfers to/from Peripherals such as USART, SSC and SPI
Two address pointers/counters per channel allowing double buffering
AT32UC3A
153
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