ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 171
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 171 of 826
- Download datasheet (20Mb)
22.3.2
22.3.3
22.4
22.4.1
32058J–AVR32–04/11
Functional Description
Interrupt Lines
Power and Clock Management
Pull-up Resistor Control
•
•
•
•
The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt
requires the interrupt controller to be programmed first.
The clock for the GPIO is controlled by the power manager. The programmer must ensure that
the GPIO clock is enabled in the power manager before using the GPIO. The clock must be
enabled in order to access the configuration registers of the GPIO and when interrupts are
enabled. After configuring the GPIO, the clock can be disabled if interrupts are not enabled.
The GPIO controls the I/O lines of the microcontroller. The control logic associated with each pin
is represented in the figure below:
Figure 22-1. Overview of the GPIO pad connections
Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled
or disabled by accessing the corresponding bit in PUER (Pull-up Enable Register). Control of the
pull-up resistor is possible whether an I/O line is controlled by a peripheral or the GPIO.
Number of I/O pins.
Functions implemented on each pin.
Peripheral function(s) multiplexed on each I/O pin.
Reset state of registers.
Periph. A output enable
Periph. B output enable
Periph. C output enable
Periph. D output enable
Periph. A output data
Periph. B output data
Periph. C output data
Periph. D output data
Periph. C input data
Periph. D input data
Periph. A input data
Periph. B input data
GPIO_PMR1
GPIO_PMR0
GPIO_ODER
GPIO_OVR
GPIO_GPER
GPIO_PVR
Glitch Filter
GPIO_GFER
1
0
0
1
0
1
Edge Detector
GPIO_IMR1
GPIO_IMR0
GPIO_ODMER
GPIO_IER
0
1
0
1
1
0
GPIO_PUER
AT32UC3A
Interrupt Request
PAD
171
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