ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 528
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 528 of 826
- Download datasheet (20Mb)
30.7.3.13
30.7.3.13.1 Global Interrupts
30.7.3.13.2 Pipe Interrupts
30.7.3.13.3 DMA Interrupts
32058J–AVR32–04/11
Interrupts
See the structure of the USB host interrupt system on
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
The processing host global interrupts are:
There is no exception host global interrupt.
The processing host pipe interrupts are:
The exception host pipe interrupts are:
The processing host DMA interrupts are:
There is no exception host DMA interrupt.
•the Device Connection interrupt (DCONNI);
•the Device Disconnection interrupt (DDISCI);
•the USB Reset Sent interrupt (RSTI);
•the Downstream Resume Sent interrupt (RSMEDI);
•the Upstream Resume Received interrupt (RXRSMI);
•the Host Start of Frame interrupt (HSOFI);
•the Host Wake-Up interrupt (HWUPI);
•the Pipe X interrupt (PXINT);
•the DMA Channel X interrupt (DMAXINT).
•the Received IN Data interrupt (RXINI);
•the Transmitted OUT Data interrupt (TXOUTI);
•the Transmitted SETUP interrupt (TXSTPI);
•the Short Packet interrupt (SHORTPACKETI);
•the Number of Busy Banks interrupt (NBUSYBK).
•the Underflow interrupt (UNDERFI);
•the Pipe Error interrupt (PERRI);
•the NAKed interrupt (NAKEDI);
•the Overflow interrupt (OVERFI);
•the Received STALLed interrupt (RXSTALLDI);
•the CRC Error interrupt (CRCERRI).
•the End of USB Transfer Status interrupt (EOT_STA);
•the End of Channel Buffer Status interrupt (EOCH_BUFF_STA);
•the Descriptor Loaded Status interrupt (DESC_LD_STA).
Figure 30-6 on page
AT32UC3A
504.
528
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