ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 363

• Manufacturer Part Number: ATEVK1104
• Description: KIT DEV/EVAL FOR AVR32 AT32UC3A
• Manufacturer: Atmel
• Series: AVR®32r
• Type: MCUr

Specifications of ATEVK1104

• Contents: Evaluation Board, Software and Documentation
• Processor To Be Evaluated: AT32UC3A3
• Data Bus Width: 32 bit
• Interface Type: USB, SPI, USART
• Silicon Manufacturer: Atmel
• Core Architecture: AVR
• Core Sub-architecture: AVR UC3
• Silicon Core Number: AT32UC3A3256
• Silicon Family Name: AVR
• Kit Contents: Board CD Docs
• Rohs Compliant: Yes
• For Use With/related Products: AT32UC3A3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

26.8.16
Name:
Access Type:
Offset:
Reset Value:
• DRIFT: Drift compensation
0: The USART can not recover from an important clock drift
1: The USART can recover from clock drift. The 16X clock mode must be enabled.
• RX_MPOL: Receiver Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
• RX_PP: Receiver Preamble Pattern detected
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled
1 - 15: The detected preamble length is RX_PL x Bit Period
• TX_MPOL: Transmitter Manchester Polarity
0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition.
1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition.
32058J–AVR32–04/11
31
23
15
–
–
–
7
–
0
0
1
1
USART Manchester Configuration Register
RX_PP
DRIFT
30
22
14
MAN
Read-write
0x50
0x30011004
–
–
6
–
0
1
0
1
Preamble Pattern default polarity assumed (RX_MPOL field not set)
ALL_ONE
ALL_ZERO
ZERO_ONE
ONE_ZERO
29
21
13
1
–
–
5
–
RX_MPOL
TX_MPOL
28
20
12
–
4
–
27
19
11
–
–
3
26
18
10
–
–
2
RX_PL
TX_PL
25
17
9
1
AT32UC3A
RX_PP
TX_PP
24
16
8
0
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