ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 761
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 761 of 826
- Download datasheet (20Mb)
36.10.3
36.11 SAB address map
32058J–AVR32–04/11
Boundary-Scan Chain
Note: This register is primarily intended for compatibility with other AVR32 devices. Certain oper-
ations may not function correctly when parts of the system are reset. It is generally
recommended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side
effects occur.
The Boundary-Scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atmel web site.
The Service Access Bus (SAB) gives the user access to the internal address space and other
features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32
LSBs are decoded within the slave’s address space. The SAB slaves are shown in
Table 36-17. SAB Slaves, addresses and descriptions.
CPU
APP
OCD
RSERVED
Memory Service
Unallocated
Reserved
Slave
OCD
HSB
HSB
Unit
CPU
HSB and PB buses
On-Chip Debug logic and registers
No effect
Address [35:32]
Other
0x0
0x1
0x4
0x5
0x6
Description
Intentionally unallocated
OCD registers
HSB memory space, as seen by the CPU
Alternative mapping for HSB space, for compatibility with
other AVR32 devices.
Memory Service Unit registers
Unused
AT32UC3A
Table
36-17.
761
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