ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 519
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 519 of 826
- Download datasheet (20Mb)
Figure 30-20. Example of an OUT Endpoint with 1 Data Bank
Figure 30-21. Example of an OUT Endpoint with 2 Data Banks
30.7.2.13.2 Detailed Description
30.7.2.14
32058J–AVR32–04/11
RXOUTI
FIFOCON
RXOUTI
FIFOCON
OUT
OUT
Underflow
(bank 0)
DATA
(bank 0)
DATA
The data is read by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be read by the firmware while the follow-
ing one is being written by the host. Then, when the firmware clears FIFOCON, the following
bank may already be ready and RXOUTI is set immediately.
This error exists only for isochronous IN/OUT endpoints. It raises the Underflow interrupt
(UNDERFI), what triggers an EPXINT interrupt if UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USB controller.
•when the bank is full, RXOUTI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing RXOUTI;
•the firmware can read the byte count of the current bank from BYCT to know how many bytes
•the firmware reads the data from the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware frees the bank and switches to the next bank (if any) by clearing FIFOCON.
RXOUTE = 1;
to read, rather than polling RWALL;
Data register (USB_FIFOX_DATA), until all the expected data frame is read or the bank is
empty (in which case RWALL is cleared by hardware and BYCT reaches 0);
HW
ACK
HW
ACK
SW
read data from CPU
SW
BANK 0
NAK
OUT
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
read data from CPU
SW
read data from CPU
AT32UC3A
BANK 1
SW
BANK 0
519
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