ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 72
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 72 of 826
- Download datasheet (20Mb)
13.6.4
Name:
Access Type:
•
•
•
•
•
32058J–AVR32–04/11
RESERVED: Reserved bitfields
PLLCOUNT: PLL Count
PLLMUL: PLL Multiply Factor
PLLDIV: PLL Division Factor
PLLOPT: PLL Option
31
23
15
7
-
Reserved for internal use. Always write to 0.
Specifies the number of slow clock cycles before ISR:LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiting a sleep mode.
These bitfields determine the ratio of the PLL output frequency (voltage controlled oscillator frequency f
oscillator frequency:
If PLLOPT[1] field is set to 0:
f
If PLLOPT[1] field is set to 1:
f
Note that the MUL field cannot be equal to 0 or 1, or the behavior of the PLL will be undefined.
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range.
PLLOPT[1]: Enable the extra output divider.
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time).
f
f
PLL
PLL
VCO
VCO
RESERVED
PLL Control
= f
= f
= (PLLMUL+1)/(PLLDIV) • f
= 2*(PLLMUL+1) • f
VCO.
VCO
/ 2
.
30
22
14
6
-
PLL0,1
Read/Write
RESERVED
RESERVED
OSC
if PLLDIV = 0.
29
21
13
5
-
OSC
if PLLDIV > 0.
28
20
12
4
PLLOPT
27
19
11
3
PLLCOUNT
26
18
10
2
PLLMUL
PLLDIV
PLLOSC
25
17
9
1
VCO
AT32UC3A
) to the source
PLLEN
24
16
8
0
72
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