ATEVK1104 Atmel, ATEVK1104 Datasheet - Page 557
![KIT DEV/EVAL FOR AVR32 AT32UC3A](/photos/9/20/92035/atevk1104_sml.jpg)
ATEVK1104
Manufacturer Part Number
ATEVK1104
Description
KIT DEV/EVAL FOR AVR32 AT32UC3A
Manufacturer
Atmel
Series
AVR®32r
Type
MCUr
Datasheets
1.ATAVRONE-PROBECBL.pdf
(16 pages)
2.ATEVK1104.pdf
(826 pages)
3.ATEVK1104.pdf
(90 pages)
4.ATEVK1104.pdf
(6 pages)
5.ATEVK1104.pdf
(12 pages)
Specifications of ATEVK1104
Contents
Evaluation Board, Software and Documentation
Processor To Be Evaluated
AT32UC3A3
Data Bus Width
32 bit
Interface Type
USB, SPI, USART
Silicon Manufacturer
Atmel
Core Architecture
AVR
Core Sub-architecture
AVR UC3
Silicon Core Number
AT32UC3A3256
Silicon Family Name
AVR
Kit Contents
Board CD Docs
Rohs Compliant
Yes
For Use With/related Products
AT32UC3A3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATEVK1104
Manufacturer:
Atmel
Quantity:
135
- ATAVRONE-PROBECBL PDF datasheet
- ATEVK1104 PDF datasheet #2
- ATEVK1104 PDF datasheet #3
- ATEVK1104 PDF datasheet #4
- ATEVK1104 PDF datasheet #5
- Current page: 557 of 826
- Download datasheet (20Mb)
30.8.2.2
Offset:
Register Name:
Access Type:
Reset Value:
• SUSP: Suspend Interrupt Flag
Set by hardware when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This trig-
gers a USB interrupt if SUSPE = 1.
Shall be cleared by software (by setting the SUSPC bit) to acknowledge the interrupt.
Cleared by hardware when a Wake-Up interrupt (WAKEUP) is raised.
• SOF: Start of Frame Interrupt Flag
Set by hardware when a USB “Start of Frame” PID (SOF) has been detected (every 1 ms). This triggers a USB interrupt if
SOFE = 1. The FNUM field is updated.
Shall be cleared by software (by setting the SOFC bit) to acknowledge the interrupt.
• EORST: End of Reset Interrupt Flag
Set by hardware when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE = 1.
Shall be cleared by software (by setting the EORSTC bit) to acknowledge the interrupt.
• WAKEUP: Wake-Up Interrupt Flag
Asynchronous interrupt.
Set by hardware when the USB controller is reactivated by a filtered non-idle signal from the lines (not by an upstream
resume). This triggers an interrupt if WAKEUPE = 1.
Shall be cleared by software (by setting the WAKEUPC bit) to acknowledge the interrupt (USB clock inputs must be
enabled before).
Cleared by hardware when a Suspend interrupt (SUSP) is raised.
32058J–AVR32–04/11
EP3INT
31
23
15
ru
–
0
7
–
USB Device Global Interrupt Register (UDINT)
DMA6INT
EP2INT
UPRSM
14
30
22
ru
ru
ru
0
–
0
6
0
DMA5INT
EORSM
EP1INT
29
21
13
ru
ru
ru
0
–
0
5
0
0x0004
UDINT
Read-Only
0x00000000
DMA4INT
WAKEUP
EP0INT
28
20
12
ru
ru
ru
0
0
4
0
DMA3INT
EORST
27
19
11
ru
ru
0
–
3
0
DMA2INT
EP6INT
SOF
26
18
10
ru
ru
ru
0
0
–
2
0
DMA1INT
EP5INT
25
17
ru
ru
0
0
9
–
1
–
AT32UC3A
EP4INT
SUSP
24
16
ru
ru
–
0
8
–
0
0
557
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