AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 87

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
SYNC
SYNC
SYNC
SYNC
ADR
ADR
SYNC
SYNC
SYNC
SYNC
0
7
7
7
1
7
3
7
5
15
11
cient transitions to allow self-clocking devices to remain in sync. Under these conditions
the equipment in use today will send sync characters in order to maintain character
phase.
In this case the receiver may want to recognize these characters and delete them from
the receive data. This function is available in the SCC by setting the Sync Character Load
Inhibit bit (D1) in WR3 to ‘1’. While this bit is set to ‘1’, the character about to be loaded
into the receive Data FIFO will be compared with the contents of WR6. If all eight bits
match the character, it is not loaded into the FIFO. Because the comparison is across
eight bits, this function works correctly only when the number of bits per character is the
same as the sync character length. Thus it cannot be used with 12- or 16-bit sync char-
acters.
Both leading sync characters and sync characters embedded in the data will be properly
removed in the case of an 8-bit sync character, but only the leading sync characters may
be properly removed in the case of a 6-bit sync character. Care must be exercised in us-
ing this feature because sync characters not transferred to the receive Data FIFO will
automatically be excluded from CRC calculation. This works properly only in the 8-bit
case.
SYNC
SYNC
SYNC
SYNC
ADR
ADR
SYNC
SYNC
SYNC
SYNC
1
6
6
6
0
6
2
6
4
14
10
Figure 4–23. SYNC Character Programming
SYNC
SYNC
SYNC
SYNC
ADR
ADR
SYNC
SYNC
SYNC
SYNC
D
D
1
7
7
5
5
5
5
5
1
5
3
13
9
D
D
6
6
SYNC
SYNC
SYNC
SYNC
ADR
ADR
SYNC
SYNC
SYNC
SYNC
D
D
1
5
5
4
4
D
D
4
4
4
0
4
2
12
8
4
4
D
D
3
3
SYNC
SYNC
SYNC
ADR
SYNC
SYNC
SYNC
SYNC
D
D
1
X
1
2
2
3
3
3
3
3
1
11
7
D
D
1
1
D
SYNC
SYNC
SYNC
ADR
D
SYNC
SYNC
SYNC
SYNC
0
0
1
X
1
2
2
2
2
2
0
10
6
SYNC
SYNC
SYNC
ADR
SYNC
SYNC
SYNC
1
X
X
1
1
1
1
1
1
9
5
SYNC
SYNC
SYNC
ADR
SYNC
SYNC
SYNC
1
X
X
0
0
0
0
0
0
8
4
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
SDLC (ADDRESS RANGE)
MONOSYNC, 8 BITS
MONOSYNC, 6 BITS
BISYNC, 16 BITS
BISYNC, 12 BITS
SDLC
AMD
4–35