AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 48

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
RTxC
PCLK
WAIT
In this mode, the W/REQ pin carries the Wait signal, and is open-drain when inactive and
Low when active. When the processor attempts to read data from the Receive Data FIFO
and it is empty, the SCC will assert W/REQ until a character has reached the top of the
FIFO. This allows the use of a block-move instruction to transfer the receive data. W/REQ
will go active in response to RD going active, but only if RR8 (Receive Buffer) is being
accessed, either directly or via the pointers. The W/REQ pin is released in response to
the falling edge of PCLK. Details of the timing are shown in Figure 3–7.
3.9.3
The two DMA request pins, W/REQ and DTR/REQ, can be programmed to be used as
DMA requests. The W/REQ pin can be used as either a transmit or a receive request, but
the DTR/REQ pin can be used only as a transmit request. Hence, for full-duplex opera-
tion, the W/REQ pin should be used for receive and the DTR/REQ pin used for transmit.
These modes are described below.
3.9.3.1
The DMA Request on Transmit function using the W/REQ pin is enabled by programming
WR1 as shown below.
TRxC
PCLK
WAIT
1
2
DMA Requests
DMA Request on Transmit (Using W/REQ)
3
WR1—DMA on Transmit Function Selection
Figure 3–6. Wait on Transmit Timing
Figure 3–7. Wait on Receive Timing
D7 D6 D5 D4 D3 D2 D1 D0
1
4
1
0
5...8
?
?
9
?
?
10
?
ASYNC Modes
11
ASYNC Modes
SYNC Modes
12
AMD
SYNC Modes
13
3–17