AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 125

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
Bit 3: Transmit Enable
Data is not transmitted until this bit is set, and the TxD output sends continuous ‘1’s un-
less Auto Echo mode or SDLC Loop mode is selected. If this bit is reset after transmis-
sion has started, the transmission of data or sync characters is completed. If the
transmitter is disabled during the transmission of a CRC character, sync or flag charac-
ters are sent instead of CRC. This bit is reset by a channel or hardware reset.
Bit 2: SDLC /CRC-16
This bit selects the CRC polynomial used by both the transmitter and receiver. When set,
the CRC-16 polynomial is used; when reset, the SDLC polynomial is used. The SDLC/
CRC polynomial must be selected when SDLC mode is selected. The CRC generator and
checker can be preset to all ‘0’s or all ‘1’s, depending on the state of the Preset 1/Preset
0 bit in WR10.
Bit 1: Request To Send
This is the control bit for the RTS pin. When the RTS bit is set, the RTS pin goes Low;
when reset RTS goes High. In the Asynchronous mode with the Auto Enables bit set,
RTS goes High only after all bits of the character have been sent and the transmit buffer
is empty. In synchronous modes or the Asynchronous mode with auto enables off, the pin
directly follows the state of this bit. This bit is reset by a channel or hardware reset.
Bit 0: Transmit CRC Enable
This bit determines whether or not CRC is calculated on a transmit character. If this bit is
set at the time the character is loaded from the transmit buffer to the Transmit Shift regis-
ter, CRC is calculated on that character. CRC is not automatically sent unless this bit is
set when the transmit underrun exists.
6.2.7
WR 6 is programmed to contain the transmit sync character in the Monosync mode. The
first byte of a 16-bit sync character in the External Sync mode. WR6 is not used in asyn-
chronous modes. In the SDLC modes, it is programmed to contain the secondary address
field used to compare against the address field of the SDLC Frame. In SDLC mode, the
SCC does not automatically transmit the station address at the beginning of a response
frame. Bit positions for WR6 are shown in Figure 6–7.
Write Register 6 (Sync Characters or SDLC
Address Field)
AMD
6–15