AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 84

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
nects TxD from RxD. To ensure proper loop operation after the SCC goes off the loop,
and until the external relays take the SCC completely out of the loop, the SCC should be
programmed for mark idle instead of Flag idle. When the SCC goes off the loop, the On–
Loop bit is reset.
4.9.2.1
To go off the loop in an orderly manner requires actions similar to those taken to go on
the loop. First, the Go Active On Poll bit must be set to ‘0’ and any transmission in pro-
gress completed, if the SCC is currently sending on the loop. This will be indicated by the
Loop Sending bit in RR10 being set to ‘0’. Once the SCC is not sending on the loop, exit
from the loop is accomplished by setting the Loop Mode bit in WR10 to ‘0’, and at the
same time writing the Abort/Flag on Underrun and Mark/Flag idle bits with the desired
values. The SCC will revert to normal SDLC operation as soon as an EOP is received, or
immediately, if the receiver is already in Hunt mode because of the receipt of an EOP.
Note that the Break/Abort and Hunt bits in RR0 will be set to ‘1’ and the On Loop bit in
RR10 will be set to ‘0’ when EOP is detected.
If SDLC loop mode is enabled by the Go Active on Poll bit (D4) in WR10 and the station
receives an EOP, the receiver will enter Hunt Mode. When the receiver is in Hunt Mode it
is not possible to take the station off the loop unless data has been transmitted; i.e., a flag
has been detected.
4.9.3
The initialization sequence for the SCC in SDLC Loop mode is similar to the sequence
used in SDLC mode, except that it is somewhat longer. The processor should program
WR4 first, to select SDLC mode, and the WR10 to select the CRC preset value, and pro-
gram the Mark/Flag Idle bit. The Loop Mode and Go Active On Poll bits in WR10 should
not be set to ‘1’ yet. The flag is written in WR7 and the various options are selected in
WR3 and WR5. At this point the other registers should be initialized as necessary, then
the Loop Mode bit (D1) in WR10 should be set to ‘1’. When all of this is complete, the
transmitter may be enabled by setting bit D3 of WR5 to ‘1’. Now that the transmitter is
enabled, the CRC generator may be initialized by issuing the Reset Tx CRC Generator
command in WR0. The receiver is enabled by setting the Go Active on Poll bit (D4) in
WR10 to ‘1’.
4.9.4
The SCC allows the user the option of using NRZI in SDLC Loop mode by programming
WR10 appropriately. With NRZI encoding, the outputs of secondary stations in the loop
may be inverted from their inputs because of messages that they have transmitted. Re-
moving the stations from the loop (removing the one-bit time delay) may cause problems
further down the loop because of extraneous transitions on the line. The SCC avoids this
problem by making transparent adjustments at the end of each frame it sends in re-
sponse to an EOP.
A response frame from the SCC is terminated by a flag and an EOP. Normally, the flag
and the EOP share a zero, but if such sharing would cause the RxD and TxD pins to be
of opposite polarity after the EOP, the SCC adds another zero between the flag and the
EOP. This causes an extra line transition so that RxD and TxD are identical after the EOP
is sent. This extra zero is completely transparent because it means only that the flag and
the EOP no longer share a zero. All that a proper loop exit needs, therefore, is the re-
moval of the one-bit time delay.
4.10
4.10.1
Receiver operation in Synchronous modes begin in a Hunt mode where the communica-
tions line is monitored for a synchronizing pattern on a bit-by-bit basis. The receiver may
be placed in Hunt mode by having the processor issue the Enter Hunt Mode command
4–32
Off Loop Programming Sequence
SDLC Loop Initialization
SDLC Loop NRZI Encoding Enabled
SYNCHRONOUS MODE OPERATION
Receiver Operation
Data Communication Modes Functional Description