AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 38

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
Each SCC on the daisy chain uses PCLK to latch the state of the Interrupt Acknowledge
signal, INTACK. If a Low INTACK is latched, then the present cycle is an interrupt ac-
knowledge cycle and the daisy chain determines which interrupt source is being acknowl-
edged in the following way. Any interrupt source that has an interrupt pending and is not
masked from the chain will hold its IEO line low. Similarly, sources that are currently un-
der service will also hold their IEO lines low.
All other interrupt sources make IEO follow IEI. The result is that only the highest priority,
unmasked source with an interrupt pending will have a high IEI input. This SCC will be
allowed to transfer its vector to the system bus when the RD strobe is issued during the
interrupt acknowledge cycle.
To ensure that the daisy chain has settled by the time RD gates the vector onto the bus,
the SCC requires a delay between falling edge of INTACK and the falling edge of RD (AC
timing parameter #38, TdlAi(RD)). The internal daisy chain may be controlled by the MIE
bit in WR9. This bit, when reset, has the same effect as pulling the IEI Low, thus disabling
all interrupt requests.
5 V
IEI
RECEIVER CHANNEL A
IP
IEI
INT
INTACK
INTACK
INTERRUPT
SCC
A
IE
INTACK
IEO
INT
IUS
IEO
Figure 3–3. External Daisy Chain
Figure 3–4. Internal Daisy Chain
IEI
INT
IEI
TRANSMIT CHANNEL A
IP
SCC
B
INTACK
INTACK
INTERRUPT
IEO
IE
INTERRUPT VECTOR
INT
IUS
IEO
IEI
VIS
INT
SCC
C
INTACK
IEO
IEI
CHANNEL B INTERRUPT
IP
EXTERNAL/STATUS
INTACK
IEI
INT
IE
SCC
DLC
MIE
NV
D
INTACK
INT IEO
IUS
IEO
AMD
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