AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 147

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
6.3.7
RR8 is the Receive Data register.
6.3.8
RR10 contains some miscellaneous status bits. Unused bits are always ‘0’. Bit positions
for RR10 are shown in Figure 6–24.
Bit 7: One Clock Missing
While operating in the FM mode, the DPLL sets this bit to ‘1’ when it does not see a clock
edge on the incoming lines in the window where it expects one. This bit is latched until
reset by a Reset Missing Clock or Enter Search Mode command in WR14. In the NRZI
mode of operation and while the DPLL is disabled, this bit is always ‘0’.
Bit 6: Two Clocks Missing
While operating in the FM mode, the DPLL sets this bit to ‘1’ when it does not see a clock
edge in two successive tries. At the same time the DPLL enters the Search mode. This bit
is latched until reset by a Reset Missing Clock or Enter Search Mode command in WR14.
In the NRZI mode of operation and while the DPLL is disabled, this bit is always ‘0’.
Bit 4: Loop Sending
This bit is set to ‘1’ in SDLC Loop mode while the transmitter is in control of the Loop, that
is, while the SCC is actively transmitting on the loop. This bit is reset at all other times.
This bit can be polled in SDLC mode to determine when the closing flag has been sent.
Bit 1: On Loop
This bit is set to ‘1’ while the SCC is actually on-loop in SDLC Loop mode. This bit is set
to ‘1’ in the X21 mode (Loop mode selected while in monosync) when the transmitter
goes active. This bit is ‘0’ at all other times. This bit can also be polled in SDLC mode to
determine when the closing flag has been sent.
Read Register 8
Read Register 10
D
7
Figure 6–24. Read Register 10
D
6
D
5
D
4
D
3
D
2
D
1
D
0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clock Missing
AMD
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