AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 44

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

I/O Programming Functional Description
3.8
The External/Status Interrupts are globally enabled via WR1 and may be individually en-
abled via WR15 as shown below. The External/Status interrupt sources are: 1) Zero
Count, 2) DCD, 3) SYNC/HUNT, 4) CTS, 5) Tx Underrun/EOM, and 6) BREAK/ABORT.
The individual External/Status Interrupt enable bits in WR15 control whether or not
latches will be present in the path from the source of interrupt to the status bit in RR0. If
an individual enable bit in WR15 is set to ‘0’, the latches are not present in the signal path
and the value read in RR0 reflects the current status. An interrupt source whose individ-
ual enable bit in WR15 is set to ‘0’ is not a source of External/Status interrupts even
though the External/Status Master Interrupt Enable bit is set to ‘1’ in WR1 (D0). When an
individual enable bit in WR15 is set to ‘1’, the latch is present in the signal path.
The latches for the sources of External/Status interrupts are not independent. Rather,
they all close at the same time as a result of a state change by one of the sources of in-
terrupt. Thus, a read of RR0 returns the current status for any bits whose individual en-
able bit in WR15 is set to ‘0’, and either the current state or the latched state of the re-
mainder of the bits. To guarantee the current status, the processor should issue a Reset
External/Status Interrupts Command in WR0 to open the latches.
The External/Status IP in RR3 is set by the closing of the latches and remains set for as
long as they are closed. If the master External/Status Interrupt enable bit is not set, the IP
will never be set, even though the latches may be present in the signal paths and working
as described. Because the latches close on the current status but give no indication of
change, the processor must maintain a copy of RR0 in memory. When the SCC gener-
ates an External/Status interrupt, the processor should read RR0 and determine which
condition changed state and take the appropriate action. The copy of RR0 in memory
must then be updated and the Reset External/Status Interrupt Command issued.
Care must be taken in writing the interrupt service routine for the External/Status inter-
rupts because it is possible for more than one status condition to change state at the
same time. All of the latched bits in RR0 should be compared to the copy of RR0 in mem-
ory. If none have changed and the ZC interrupt is enabled, the Zero Count condition
caused the interrupt.
3.8.1
The SYNC/HUNT status bit reports the Hunt state of the receiver in SDLC and Synchro-
nous modes. This bit is set to ‘1’ when the processor issues the Enter Hunt Command,
and is reset to ‘0’ when character synchronization is established by the receiver. If the
SYNC/HUNT IE bit in WR15 is set to ‘1’, the External/Status latches close, and an Exter-
nal/Status interrupt will be generated on both the Low-to-High and High-to-Low transitions
of the SYNC/HUNT status bit.
EXTERNAL/STATUS INTERRUPTS
Sync/Hunt
BREAK/
ABORT
D7
IE
D7
EOM IE
Undr/
Tx
D6
D6
WR15 and WR1—Register Layout
CTS
D5
IE
D5
SYNC/
HUNT
D4
D4
IE
DCD
D3
IE
D3
D2
D2
Count
Zero
IE
D1
D1
Status
Ext/
MIE
D0
D0
AMD
3–13