AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 41

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
3.5.4
If the No Vector bit in WR9 (D1) is set to ‘1’, the SCC will not place the vector on the data
bus during the Interrupt Acknowledge cycle. An external interrupt controller must then
vector the code to the interrupt routine. The interrupt routine must then read RR2 from
Channel B to read the status. This is the same as the case of an interrupt without an ac-
knowledge except that INTACK needs to be generated. The IUS is set as before, and the
vector read in RR2 will not change until the Reset IUS command in WR0 is issued.
3.5.5
The NMOS SCC’s ability to mask lower priority interrupts is done via the IUS bit. This bit
is internal to the SCC and is not observable by the processor. Being able to automatically
mask lower priority interrupts allows a modular approach to coding interrupt routines.
However, using the masking capabilities of the NMOS SCC requires that the INTACK cy-
cle be generated. In applications where an external interrupt controller is being used to
supply the vector, having to generate INTACK through external hardware, in order to use
this capability, is an unnecessary expense.
On the CMOS SCC if bit D5 in WR9 is set to ‘1’, the INTACK cycle does not need to be
generated in order to have the IUS bit set and must be tied High. When this bit is set and
an interrupt occurs, reading RR2 will cause the IUS bit to be set for the highest priority IP.
After the interrupting condition is cleared, the routine can then read RR3 to determine if
any other IPs are set and clear them. At the end of the interrupt routine, a Reset IUS
command must be issued to unlock the internal daisy chain, and reset the IUS bit. Note
that in this mode the No Vector and Vector Includes Status bits in WR9 are ignored.
3.6
Four receive interrupt modes are available on the SCC. These four modes are: 1) Re-
ceive Interrupts Disabled, 2) Interrupt on First Character or Special Condition, 3) Interrupt
on All Received Characters or Special Condition, and 4) Receive Interrupt on Special
Condition Only.
The mode selected is controlled by bits D4 and D3 of WR1. The Special Condition inter-
rupts are: Receive FIFO Overrun, CRC/Framing Error, EOF, and Parity. The Parity condi-
tion can either be included as a Special Condition or not depending on bit D2 in WR1.
The Special Condition status can be read via RR1.
3.6.1
This mode prevents the receiver from requesting an interrupt. It is used in a polled envi-
ronment where either RR0 or the modified vector in RR2 (Channel B) is read for status.
When either RR0 or RR2 indicates that a received character has reached the top of the
Receive Data FIFO, the status should be read first and then RR8 because reading RR8
moves the next character in the Receive Data FIFO and Error FIFO up one location. If
status is read after the data are read, the error data belonging (if any) to the next charac-
ter in the FIFO will also be included. If, however, operations are being performed rapidly
enough so that the next character has not yet been received, then the status will remain
valid.
Although the Receiver interrupts are disabled, a Special Condition can still provide a
unique vector status in RR2.
3.6.2
This mode is designed for use with an external DMA Controller. After this mode is se-
lected, the first character received, or the first character already stored in the Receive
Data FIFO, will set the Receiver IP. This IP will be reset when this character is removed
from the SCC, and no further receive interrupts will occur until the processor issues an
Enable Interrupt on Next Receive Character command in WR0 or until a Special Condi-
tion interrupt occurs.
3–10
Interrupt With Acknowledge Without Vector
Lower Priority Interrupt Masking
RECEIVE INTERRUPTS
Receive Interrupts Disabled
Receive Interrupt on First Character or Special
Condition
I/O Programming Functional Description