AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 37

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
3.5
Interrupts from the SCC may be acknowledged with a vector, acknowledged without a
vector, or not acknowledged at all. WR2 is used to hold the interrupt vector returned dur-
ing an interrupt acknowledge cycle. This vector register can be shared among multiple
interrupt sources; some bits of the vector can be encoded with information that identifies
the interrupt source.
Three bits in WR9 determine whether or not a vector is placed on the bus and whether or
not status is included. The Vector Includes Status (VIS) bit (D0) enables status informa-
tion to be included in the vector, the Status High/Status Low bit (D4) determines which
bits of the vector are encoded as shown in Figure 3–2, and the No Vector (NV) bit (D1)
enables or disables placing the vector on the bus in response to an interrupt acknowledge
cycle.
In addition, the SCC can share a common interrupt request line to the processor. An ex-
ternal interrupt priority daisy chain, constructed using IEI and IEO on each SCC, is used
to resolve contention when multiple SCC devices share an interrupt request line. This ca-
pability eliminates the need for separate interrupt controllers. An interrupt acknowledge
cycle that includes the generation of an explicit Interrupt Acknowledge signal (INTACK) is
used to select the highest priority SCC asserting INT. Figure 3–3 shows a typical arrange-
ment for four SCCs, labeled A through D, on the daisy chain, where A has the highest
priority and D has the lowest priority.
3.5.1
The SCC has an internal priority resolution method to allow the highest priority interrupt to
be serviced first. It uses a daisy chain technique of priority interrupt control whereby other
SCC devices are connected together via an external interrupt daisy chain formed with
their Interrupt Enable Input (IEI) and Interrupt Enable Output (IEO) pins. The six interrupt
sources within each SCC are similarly chained together as shown in Figure 3–4 with
Channel A interrupts being higher-priority than any Channel B interrupts, and with the Re-
ceiver, Transmitter, and External/Status interrupts prioritized in that order within each
channel. The overall effect is a daisy chain connecting all internal and external interrupt
sources that allows higher priority interrupt sources to pre-empt lower priority sources
and, in the case of simultaneous interrupt requests, determines which request will be ac-
knowledged.
3–6
INTERRUPT OPERATIONS
Multiple Interrupt Priority Resolution
V3
V4
0
0
0
0
1
1
1
1
Figure 3–2. Interrupt Vector Modification
V2
V5
0
0
1
1
0
0
1
1
V1
V6
0
1
0
1
0
1
0
1
Status High/Status Low = 0
Status High/Status Low = 1
Ch B Transmit Buffer Empty
Ch B External/Status Change
Ch B Receive Character Available
Ch B Special Receive Condition
Ch A Transmit Buffer Empty
Ch A External/Status Change
Ch A Receive Character Available
Ch A Special Receive Condition
I/O Programming Functional Description