AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 43

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
I/O Programming Functional Description
the status and unlock the FIFO by issuing an Error Reset command. DMA transfer of the
receive characters will then resume.
If Receive Interrupts on Special Condition Only is enabled and a Special Condition occurs
then, if a modified vector is read from RR2 or as the output of an INTACK cycle, that vec-
tor may indicate Receive Character Available instead of Receive Special Condition. The
reason is that if a character is received and simultaneously the Special condition occurs,
the priority circuitry gives Receive Character Available the highest priority and thus over-
rides the Special Condition. Note that a Receive Character Available itself does not gen-
erate an interrupts if Receive Interrupts on Special Condition Only is enabled. It is the
Special Condition that generates the interrupt.
In Am85C30, if the 10 x 19 Frame Status FIFO is enabled, the 3 byte Receive (Rx) FIFO
never locks. However, the DMA is disabled (only on overrun special condition), i.e. over-
runs do not lock the Rx FIFO, but do disable DMA. Interrupts are generated and remain
active until RESET ERROR command is issued.
3.7
TRANSMIT INTERRUPTS
The transmit interrupt request has only one source; it can be set only when WR8 (Trans-
mit Buffer) goes from full to empty. Note that this means that the transmit interrupt will not
be set until after the first character is written to the SCC.
Transmit Interrupt occurs, if enabled, when the transmit buffer goes from a full to an
empty state, which happens when the buffered character is loaded into the transmit shift
register from the transmit buffer. In SDLC or other synchronous modes with the CRC gen-
erator enabled, the two CRC bytes that are attached to the data forces the transmit shift
register to be full. When the second byte of the CRC is loaded into the transmit shift regis-
ter, a Transmit Interrupt is generated if it is enabled.
Transmit interrupts are controlled by the Transmit Interrupt Enable bit in WR1 (D1). If the
interrupt capabilities of the SCC are not required, polling may be used. This is selected by
disabling the transmit interrupts and polling the Transmit Buffer Empty bit in RR0. When
the Transmit Buffer Empty bit is set, a character may be written to the SCC without fear of
writing over previous data. Another way of polling the SCC is to enable the transmit inter-
rupt and then reset the MIE bit in WR9. The processor may then poll the IP bits in RR3A
to determine when the Transmit Buffer is empty. Transmit interrupts should also be dis-
abled in the case of DMA transfer of the transmitted data.
While the transmit interrupts are enabled, the SCC will set the Transmit IP whenever the
Transmit Buffer becomes empty. This means that the Transmit Buffer must have been full
before the Transmit IP can be set. Thus, when the transmit interrupts are first enabled,
the Transmit IP will not be set until after the first character is written to the SCC.
In SDLC and Synchronous modes, one other condition can cause the Transmit IP to be
set. This occurs at the end of the CRC transmission. When the last bit of CRC has
cleared the Transmit Shift Register and the flag or sync character is loaded into the
Transmit Shift Register, the SCC will set the Transmit IP. Data for the new frame or mes-
sage to be transmitted may be written at this time. The Transmit Buffer Empty bit will be
set after each Transmit IP. At the end of a frame or message block of data where CRC is
to be sent next, no data will be written to the SCC (a Reset Tx IP command can be issued
to clear the Transmit IP). The Transmitter will then underflow, the CRC will be sent and
the Transmit Buffer Empty bit will be reset (indicating that data should not be written to
the SCC at this time). The Transmit Underrun/EOM bit will be set when the CRC is
loaded to indicate that the transmitter has underflowed. After the last bit of CRC has
cleared the Transmit Shift Register and the flag or sync character is loaded into the
Transmit Shift Register the SCC will set the Transmit IP. The Transmit Buffer Empty bit
will be set at this time, indicating that data for the new frame should be written. The
Transmit IP is reset either by writing data to WR8 or by issuing the Reset Transmit IP
Command in WR0. Ordinarily, the response to a transmit interrupt is to write more data to
the SCC; however, at end of a frame or meassage block of data where CRC is to be sent
next, the Reset Transmit IP command should be issued in lieu of data.
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