AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 30

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
If both bits D0 and D2 of WR15 are set to ‘1’ then the Am85C30 register map is as shown
in Table 2–6.
2.6
The SCC may be reset by either hardware or software. A hardware reset occurs when
RD and WR are both Low, simultaneously regardless of the state of the CE input, which
is normally an illegal condition. As long as both RD and WR are Low, the SCC recognizes
the reset condition. Once this condition is removed, however, the reset condition is as-
serted internally for an additional four to five PCLK cycles. During this time, any attempt
to access the SCC will be ignored. However a hardware reset does not clear the receive
FIFO, therefore it may be necessary to perform a few dummy reads immediately after a
2–12
With the Point High command:
A/B
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
RESET
Table 2–6. Register Set—All Enhancements Enabled
PNT
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
2
PNT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
PNT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
WRITE
WR0B
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
WR0A
WR1A
WR2
WR3A
WR4A
WR5B
WR6A
WR7A
WR8B
WR9
WR10B
WR11B
WR12B
WR13B
WR14B
WR15B
WR8A
WR9
WR10A
WR11A
WR12A
WR13A
WR14A
WR15A
READ
RR0B
RR1B
RR2B
RR3B
RR4B(WR4B)
RR5B(WR5B)
RR6B
RR7B
RR0A
RR1A
RR2A
RR3A
RR4A(WR4A)
RR5A(WR5A)
RR6A
RR7A
RR8B
RR9B(WR3B)
RR10B
RR11B(WR10B)
RR12B
RR13B
RR14B(WR7’B)
RR15B
RR8A
RR9A(WR3A)
RR10A
RR11A(WR10A)
RR12A
RR13A
RR14A(WR7’A)
RR15A
System Interface