AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 25

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

System Interface
INTACK
D
0
PCLK
– D
IEO
INT
RD
2.5
SDLC/HDLC enhancements on the Am85C30 are enabled or disabled via bits D2 and D0
in WR15. Bit D2 determines whether or not the 10x19-bit SDLC/HDLC frame status FIFO
is enabled while bit D0 determines whether or not other SDLC/HDLC mode enhance-
ments are enabled via WR7’. Table 2–3 shows what functions on the Am85C30 are en-
abled when these bits are set.
When bit D2 of WR15 is set to ‘1’, two additional registers (RR6 and RR7) per channel
specific to the 10x19-bit frame status FIFO are made available. The Am85C30 register
map when this function is enabled is shown in Table 2–4.
IEI
A/B, D/C
7
INTACK
D
0
- D
WR
CE
7
Am85C30 Enhancement Register Access
Figure 2–3. Interrupt Acknowledge Cycle
Figure 2–2. SCC Write Cycle
Address Valid
Data Valid
Vector
10216A-010A
AMD
2–7