AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 64

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
4.6
4.6.1
In Asynchronous mode, the receiver establishes bit and character synchronization by
sensing the High-to-Low transition of the Start-bit for each character. When the Start-bit is
detected a clock circuit is initiated and the receiver waits one-half a bit time before sam-
pling RxD again to ensure that RxD is still Low. If RxD is Low, the receiver assumes that
it is the middle of the Start-bit and one bit time later begins to assemble the specified
number of data and Parity (if enabled) bits. During reception, the Start and Stop bits are
stripped leaving only the data and Parity (if enabled and with less than 8 bits/character
option selected). Once the character is assembled, the receiver samples RxD one more
bit time. If RxD is Low, the Framing Error bit is set and is passed to the Receive Error
FIFO at the same time the character is transferred to the Receive Data FIFO. If the RxD
is High, the receiver returns to the quiescent marking state until the next High-to-Low
transition is detected on the RxD pin.
In this mode, serial data enters the 3-bit delay if the character length of seven or eight bits
is selected. If a character length of five or six bits is selected, data enters the Receive
Shift Register directly.
4.6.1.1
The initialization sequence for the receiver in Asynchronous mode is: WR4 first to select
the mode, then WR3 and WR5 to select the various options. At this point, the other regis-
ters should be initialized as necessary. When all of this is complete the receiver may be
enabled by setting bit D0 of WR3 to ‘1’.
4.6.1.2
If after assembling the selected number of bits per character the Receiver finds the Stop
bit to be a ‘0’, the Framing Error bit in the Receive Error FIFO is set at the same time that
the character is transferred to the Receive Data FIFO. This error bit accompanies the
data to the top of the FIFO, where it generates a Special Condition interrupt (if enabled).
This Framing Error bit is not latched, and so must be read in RR1 before the accompany-
ing data is read in the Receive Data FIFO. Detection of a Framing Error adds an addi-
tional one-half bit to the character time so that the Framing Error is not interpreted as a
new Start bit.
4–12
Tx Underrun/EOM
RTS bit D1 WR5
RTS pin (active low)
ASYNCHRONOUS MODE OPERATION
Receiver Operation
Receiver Initialization
Framing Error
Data
Data being sent
Figure 4–10. RTS Deactivation
Data Communication Modes Functional Description
CRC
CRC
flag