AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 102

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
5.3.1
The clock source for the BRG is selected by bit D1 of WR14. When this bit is set to ‘0’,
the BRG uses the signal on the TRxC pin as its clock, independent of whether the TRxC
pin is a simple input or part of the crystal oscillator circuit. When this bit is set to ‘1’, the
BRG is clocked by PCLK. Note that in order to avoid metastable problems in the counter,
this bit should be changed only while the BRG is disabled, since arbitrarily narrow pulses
can be generated at the output of the multiplexer when it changes status.
5.3.2
The BRG is enabled while bit D0 of WR14 is set to ‘1’ and is disabled while this bit is set
to ‘0’. To prevent metastable problems when the BRG is first enabled, the enable bit is
synchronized to the BRG clock. This introduces an additional two count delay when the
BRG is first enabled as shown in Figure 5–3.
The BRG is disabled immediately when bit D0 of WR14 is set to ‘0’ and no delay is gener-
ated. The BRG may be enabled and disabled on the fly, but this delay on startup must be
taken into consideration.
Note that on the NMOS Z8530 (non-Hstep), it has been verified that if the BRG is dis-
abled and then re-enabled, the BRG down counter may become underflowed. When this
happens there will be a delay of (FFFF) (BRG clk period) = 65535 (BRG clk period)
before the down counter is loaded with the new time constant. This will delay any activity
which is controlled by the BRG.
It is important to clarify that if the underflow condition occurs, the resultant delay will occur
once. All subsequent BRG controlled delays will be per the programmed BRG count
value. In a system this one time delay may not cause a failure since activities like data
transmission do not have to be completed within a fixed time frame. If the delay happens,
the data remains in the Transmit Buffer and will be transmitted at a later time. However,
in diagnostic routines the baud rate delay can cause failures, since all activities are ex-
pected to be completed within a fixed time frame.
Therefore, in order to guarantee correct operation, the SCC BRG should be operated ac-
cording to the following guidelines:
1) If the BRG needs to be disabled, re-enable it only after a hardware reset. This is not al-
2) If the time constant has to be re-loaded, do it “on the fly” with the LSB first.
3) If the BRG has to be disabled and re-enabled without a hardware reset, then the baud
5–8
ways possible or desirable, but will guarantee that no underflow condition will occur.
rate may be delayed one time by 65535 * (BRG clk period).
If MSB is not being used (MSB = 00H), then the maximum delay for the new baud
rate will be:
(old LSB) (BRG Clock cycle)
If both MSB and LSB are being used, then loading the new LSB first might generate
an intermediate baud rate determined by the new LSB and old MSB time
constants. After the new MSB is loaded the worst case delay for the new baud rate
will be:
Max[(old MSB,old LSB),(old MSB,new LSB)] (BRG clock cycle)
If during the transition from the old baud rate to the new one the baud rate is not
being used, and the above delays are taken into consideration, then loading the
time constant “on the fly” will not cause any problems and will guarantee that no
underflow condition will occur.
BRG Clock Source
BRG Enabling/Disabling
Support Circuitry Programming