AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 127

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
6.2.8
In the Nmos Am8530H, the use of this register differs depending on the mode the SCC is
programmed in. In Monosync mode, WR7 is programmed with the receive sync charac-
ter; in BISYNC, it is programmed with the second byte (the last 8 bits) of the 16-bit sync
character. In SDLC modes, WR7 is programmed with the flag character (01111110).
Note, however, that WR7 may hold the receive sync character or flag if one of the special
versions of the External Sync mode is selected.
Write Register 7 (Special SDLC Enhancement Register)
In the CMOS Am8530, special SDLC options are provided that enable the user to more
effectively interface to the Am85C30. These options are available to the user if the previ-
ously unused bit, D0 of WR15, is set to ‘1’. When this bit is set, and the SCC is pro-
grammed for SDLC operation, an access to WR7 accesses a different register which
allows the programming of these options. This register is referred to as WR7’ (WR7
prime). Resetting this bit (D0 of WR15) disables the options and the next access to WR7
is to the flag register. Therefore, the user should always program the flag character first
before setting bit D0 of WR15 to ‘1’. This register is readable by executing a read to RR14
when D0 of WR15 and D6 of WR7’ are set to ‘1’.
Note that WR7 is not used in Asynchronous mode. Bit positions for WR7 are shown in
Figure 6–8. Bit positions for WR7’ are shown in Figure 6–9 with bit descriptions given
below.
Bit 7: Not used. This bit must be programmed with ‘0’.
Bit 6: Extended Read Enable
If this bit is set to ‘1’ the user is able to read the following previously unreadable registers;
WR3, WR4, WR5 and WR10 in the CMOS SCC in each channel. These registers are
read by addressing bogus read registers RR9, RR4, RR5 and RR11, respectively.
WR7’ is updated or modified by writing to WR7 while this bit is set and is read by execut-
ing a read cycle to WR14 (RR14).
Bit 5: Receive CRC
If this bit is set to ‘1’, the last two bits of the received CRC are properly clocked into the
receive shift register and are available to the user.
D
7
Write Register 7 (Sync Character or SDLCFlag/SDLC
Option Register)
Note SDLC option register is available only in CMOS version.
D
6
D
5
D
4
D
3
D
2
Figure 6–9. Write Register 7
D
1
D
0
Auto Tx Flag
Auto EOM Reset
Auto RTS Deactivation
TxD forced high in SDLC NRZI Mode
DTR/REQ Timing Mode
Receive CRC
Extended Read Enable
This bit must always be programmed with a ‘0’
AMD
6–17