AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 47

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Each channel in the SCC has two pins, DTR/REQ and W/REQ, which may be used to
control the block transfer of data. Both pins in each channel may be programmed to act
as DMA Request signals, and one pin (W/REQ) in each channel may be programmed to
act as a Wait signal for the CPU. In either mode, it is advisable to select and enable the
mode in two separate accesses of the appropriate register. The first access should select
the mode and the second access should enable the function. This procedure prevents
glitches on the output pins. Reset forces Wait mode, with W/REQ open-drain.
3.9.1
The Wait function on transmit is selected by programming WR1 as shown below.
In this mode, the W/REQ pin carries the Wait signal, and is open-drain when inactive and
Low when active. When the processor attempts to write to WR8 (Transmit Buffer) and it is
full, the SCC will assert W/REQ until the buffer is empty. This allows the use of a block-
move instruction to transfer the transmit data. W/REQ will go active in response to WR
going active but only if WR8 (Transmit Buffer) is being accessed, either directly or via the
pointers. The W/REQ pin is released in response to the falling edge of PCLK. Details of
the timing are shown in Figure 3–6.
3.9.2
The Wait function on receive is selected by programming WR1 as shown below.
3–16
DMA REQ
Enable
Wait/
D7
Wait on Transmit
Wait on Receive
D7
DMA REQ
Funct.
Wait/
D6
WR1—Wait on Transmit Function Selection
WR1—Wait on Receive Function Selection
D6
DMA REQ
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
1
Rx/Tx
Wait/
D5
D5
WR14 Register Layout
0
0
WR1 Register Layout
D4
0
1
D4
?
?
D3
I/O Programming Functional Description
?
?
D3
?
?
Funct.
DTR/
REQ
D2
?
?
D2
?
?
D1
D1
D0
D0