AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 120

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
6.2.4
This register contains the control bits and parameters for the receiver logic as illustrated
in Figure 6–4. This register is readable by executing a Read to RR9 when D0 of WR15
and D6 of WR7’ are set to ‘1’.
Bits 7 and 6: Receiver Bits/Character
The state of these two bits determines the number of bits to be assembled as a character
in the received serial data stream. Table 6–2 lists the number of bits per character in the
assembled character format. The number of bits per character can be changed while a
character is being assembled, but only before the number of bits currently programmed is
reached. Unused bits in the Received Data Register (RR8) are set to ‘1’ in asynchronous
modes. In synchronous modes and SDLC modes, the SCC transfers an 8-bit section of
the serial data stream to the receive FIFO at the appropriate time.
Bit 5: Auto Enables
This bit programs the function for both DCD and CTS pins. CTS becomes the transmitter
enable and DCD becomes the receiver enable when this bit is set to ‘1’. However, the
Receiver Enable and Transmit Enable bits must be set before the DCD and CTS pins can
be used in this manner. When the Auto Enables bit is set to ‘0’, the DCD and CTS pins
are merely inputs to the corresponding status bits in Read Register 0. The state of DCD is
ignored in the Local Loopback mode. The state of CTS is ignored in both Auto Echo and
Local Loopback modes. If CTS disables the transmitter during a byte transmission, the
SCC will still complete the byte transfer.
Bit 4: Enter Hunt Mode
This command forces the comparison of sync characters or flags for the purpose of syn-
chronization. After reset, the SCC automatically enters the Hunt mode (except asynchro-
nous). Whenever a flag or sync character is matched, the Sync/Hunt bit in Read Register
0 is reset and, if External/Status Interrupt Enable is set, an interrupt sequence is initiated.
The SCC automatically enters the Hunt mode when an abort condition is received or
when the receiver is disabled.
Bit 3: Receiver CRC Enable
This bit is used to initiate CRC calculation at the beginning of the last byte transferred
from the Receiver Shift register to the receive FIFO. This operation occurs independently
of the number of bytes in the receive FIFO. When a particular byte is to be excluded from
CRC calculation, this bit should be reset before the next byte is transferred to the receive
FIFO. If this feature is used, care must be taken to ensure that eight bits per character is
selected in the receiver because of an inherent delay from the Receive Shift register to
the CRC checker.
This bit is internally set to ‘1’ in SDLC mode and the SCC calculates CRC on all bits ex-
cept inserted zeros between the opening and closing character flags. This bit is ignored in
asynchronous modes.
6–10
Write Register 3 (Receive Parameters and Control)
Table 6–2. Receive Bits/Character
D
0
0
1
1
7
D
0
1
0
1
6
Character Length
5 Bits/Character
7 Bits/Character
6 Bits/Character
8 Bits/Character
Register Description