AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 27

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

System Interface
Bit D0 of WR15 determines whether or not other enhancements pertinent only to SDLC/
HDLC Mode operation are available for programming via WR7 as shown below. Write
Register 7 prime (WR7 ) can be written to when bit D0 of WR15 is set to ‘1’. When this
bit is set, writing to WR7 (flag register) actually writes to WR7 . If bit D6 of this register is
set to ‘1’, previously unreadable registers WR3, WR4, WR5, WR10 are readable by the
processor. In addition, WR7 is also readable by having this bit set. WR3 is read when a
bogus RR9 register is accessed during a read cycle, WR10 is read by accessing RR11,
and WR7 is accessed by executing a read to RR14. The Am85C30 register map with bit
D0 of WR15 and bit D6 of WR7 set is shown in Table 2–5.
FIFO Enabled Enhance Enabled
WR15 bit D2
10x19-bit
1
0
0
1
1
SDLC/HDLC
WR15 D0
Table 2–3. Enhancement Options
0
1
1
1
1
Read Enable
WR7 bit D6
Extended
x
0
1
0
1
Functions Enabled
10x19-bit FIFO enhancement
enabled only
SDLC/HDLC enhancements
enabled only
SDLC/HDLC enhancements
enabled with extended read
enabled
10x19-bit FIFO and SDLC/
HDLC enhancements enabled
10x19-bit FIFO and SDLC/
HDLC enhancements with
extended read enabled
AMD
2–9