AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 124

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
Bit 7: Data Terminal Ready
This is the control bit for the DTR/REQ pin while the pin is in the DTR mode (selected in
WR14). When set, DTR is Low; when reset, DTR is High. This bit is ignored when DTR/
REQ is programmed to act as a Request pin. This bit is reset by a channel or hardware
reset.
Bits 6 and 5: TX Bits/Character 1 and 0
These bits control the number of bits in each byte transferred to the transmit buffer. Bits
sent must be right justified with least significant bits first.
The Five Or Less mode allows transmission of one to five bits per character; however, the
CPU should format the data character as shown below in Table 6–3. In the Six or Seven
Bits/Character modes, unused data bits are ignored.
Bit 4: Send Break
When set, this bit forces the TxD output to send continuous ‘0’s beginning with the follow-
ing transmit clock, regardless of any data being transmitted at the time. This bit functions
whether or not the transmitter is enabled. When reset, TxD continues to send the con-
tents of the Transmit Shift register, which might be syncs, data, or all ‘1’s. If this bit is set
while in the X21 mode (Monosync and Loop mode selected) and character synchroniza-
tion is achieved in the receiver, this bit is automatically reset and the transmitter begins
sending syncs or data. This bit can also be reset by a channel or hardware reset.
6–14
D
1
1
1
1
0
7
D
D
0
0
1
1
1
1
1
0
0
6
6
D
D
D
7
0
1
0
1
1
1
0
0
0
5
5
D
0
0
1
1
6
Table 6–3. Transmit Bits/Character
D
D
D
1
0
0
0
0
1
0
1
Character Length
5 or less bits/character
7 bits/character
6 bits/character
8 bits/character
5
4
4
Figure 6–6. Write Register 5
D
Tx 5 Bits (or less)/Character
Tx 7 Bits/Character
Tx 6 Bits/Character
Tx 8 Bits/Character
4
D
D
D
0
0
0
D
3
3
3
3
D
2
D
D
D
D
0
0
2
2
2
2
D
1
D
D
D
D
D
D
0
0
1
1
1
1
1
Tx CRC Enable
RTS
SDLC/CRC-16
Tx Enable
Send Break
DTR
D
D
D
D
D
D
0
0
0
0
0
0
Transmitter
Sends one data bit
Sends two data bits
Sends three data bits
Sends four data bits
Sends five data bits
Register Description