AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 35

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

AMD
3.4
In addition to the MIE bit that enables or disables all SCC interrupts, three control/status
bits are associated with each interrupt source internal to the SCC. These are the Interrupt
Enable (IE), the Interrupt Pending (IP), and the Interrupt Under Service (IUS) bits. Simi-
larly, lower-priority devices on the external daisy chain can be prevented from requesting
interrupts via the Disable Lower Chain bit in WR9 (D2).
3.4.1
The Interrupt Enable (IE) bits are written by the processor and serve to control interrupt
requests from each interrupt source on the SCC. If the IE bit is set to ‘1’ for an interrupt
source, then that source may cause an interrupt request providing all of the necessary
conditions are met. If the IE bit is reset, no interrupt request will be generated by that
source. The IE bits are write-only and are programmed in WR1 as follows.
3–4
INT on 1st Rx Char. or
Special Condition
INT on All Rx Char. or
Special Condition
Rx Int on Special
Condition only
Parity
Zero Count
DCD
SYNC/HUNT
CTS
Tx Underrun/EOM
Break/Abort
Transmit Buffer Empty
INTERRUPT CONTROL
Interrupt Enable Bit
Receiver Channel A
Transmit Channel A
External/Status Channel A
Receiver Channel B
Transmit Channel B
External/Status Channel B
Table 3–1. Interrupt Source Priority
Figure 3–1. SCC Interrupts
External/Status
Transmitter
Receiver
Interrupt
Sources
Interrupt
Sources
Interrupt
Source
I/O Programming Functional Description
High
Low
Interrupt
SCC