AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 21

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

CHAPTER 2
2.1
The SCC internal structure provides all the interrupt and control logic necessary to inter-
face with non-multiplexed buses. Interface logic is also provided to monitor modem or
peripheral control inputs or outputs. All of the control signals are general-purpose and can
be applied to various peripheral devices as well as used for modem control.
The center for data activity revolves around the internal read and write registers. The pro-
gramming of these registers provides the SCC with functional “personality;” i.e. register
values can be assigned before or during program sequencing to determine how the SCC
will establish a given communication protocol.
This chapter covers the details of interfacing the SCC to a system. The general timing
requirements are described but the respective data sheets must be referred to for specific
A.C. numbers.
2.2
All modes of communication are established by the bit values of the write registers. As
data are received or transmitted, read register values may change. These changed val-
ues can promote software action or internal hardware action for further register changes.
The register set for each channel includes several write and read registers. Ten write reg-
isters are used for control, two for sync character generation, and two for the on-chip
baud rate generator. Two additional write registers are shared by both channels; one is
used as the interrupt vector and one as the master interrupt control. Both registers are
accessed and shared by either channel.
Six read registers indicate status functions; two are used by the baud rate generator, and
one by the receiver buffer. The remaining two read registers are shared by both channels;
one for interrupt pending bits and one for the interrupt vector. On the Am85C30 three ad-
ditional registers are available. Refer to Chapter 4 and Chapter 6 for further details on
these registers.
Table 2–1 summarizes the assigned functions for each read and write register. Chapter 6
provides a detailed bit legend and description of each register.
System Interface
INTRODUCTION
REGISTERS
2–3