AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 63

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Data Communication Modes Functional Description
The character length may be changed at any time, but the desired length must be se-
lected before the character in the transmit buffer is transferred to the the Transmit Shift
Register. The easiest way to ensure this is to write to WR5 to change the character length
before writing the data to the transmit buffer.
4.5.2
In all modes of operation bit D0 (Parity Enable) of WR4 determines whether an additional
bit will be appended to each character sent as an indication of the “oddness” or “even-
ness” of the number of ‘1’ bits transmitted in the character. If this bit is set to ‘1’ an addi-
tional bit will be sent in addition to the number of bits specified in WR4, or by the data for-
mat used when transmitting less than five bits per character.
Bit D1 of WR4 determines the even/odd sense of this additional bit when Parity is en-
abled. If this bit is set to ‘1’, the transmitter adds a bit that makes the total number of ‘1’
bits in the character being transmitted even; if set to ‘0’, a bit will be added to make the
sum of ‘1’ bits in the character being transmitted odd.
4.5.3
The transmitter may be programmed to send a break condition (i.e., the TxD pin is pulled
Low) in all modes of operation via bit D4 of WR5. When this bit is set to ‘1’, the transmit-
ter suspends any data being transmitted at the time and sends continuous ‘0’s from the
first transmit clock edge after this command is issued, until the first transmit clock edge
after this bit is reset, at which point the transmitter continues to send the contents of the
Transmit Shift Register. The transmit clock edges referred to here are those that define
transmitted bit cell boundaries. Note that the TxD pin will be pulled Low whether or not
the transmitter is enabled.
4.5.4
There are two modem control signals associated with the transmitter on the SCC. The
RTS pin is a general-purpose output that carries the inverted state of the RTS bit in WR5
(D1), and the CTS pin is a general-purpose input to the CTS status bit in RR0 (D5). How-
ever, if the Auto Enables Mode is selected (by setting D5 of WR3 to ‘1’), CTS becomes
an enable for the transmitter. That is, if Auto Enables is on and the CTS pin is HIGH the
transmitter will be disabled; while the CTS pin is LOW the transmitter will be enabled.
Note, however, that in all modes of operation, the Transmitter Enable bit must be set be-
fore the CTS pin can be used in this manner.
If the SCC channel is programmed in Asynchronous mode, and the Auto Enable bit is set
to ‘1’, RTS will remain Low until the transmitter is completely empty and the last stop bit
has left the TxD pin. In SDLC and Synchronous modes, the RTS pin is just a general-
purpose output.
4.5.5
On the CMOS SCC, if bits D0 of WR15 and D2 of WR7’ are set to ‘1’ and the channel is
in SDLC Mode, the RTS pin may be reset early in the Tx Underrun routine and the RTS
pin will remain active until the last zero bit of the closing flag leaves the TxD pin as shown
in Figure 4–10.
Note that in order for this to function properly, bits D3 and D2 of WR10 must be set to ‘1’
and ‘0’, respectively.
Tx Parity
Break Generation
Transmit Modem Control
Auto RTS Reset
AMD
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