AM8530H AMD [Advanced Micro Devices], AM8530H Datasheet - Page 133

• Manufacturer Part Number: AM8530H
• Description: Serial Communications Controller
• Manufacturer: AMD [Advanced Micro Devices]

Register Description
AMD
Bit 2: Abort/ Flag On Underrun
This bit affects only SDLC operation and is used to control how the SCC responds to a
transmit underrun condition. If this bit is set to ‘1’ and a transmit underrun occurs, the
SCC sends an abort and a flag instead of CRC. If the bit is reset, the SCC sends CRC on
a transmit underrun. At the beginning of this 16-bit transmission, the Transmit Underrun/
EOM bit is set, causing an External/Status interrupt. The CPU uses this status, along with
the byte count from memory or the DMA, to determine whether the frame must be
retransmitted. A transmit buffer Empty interrupt occurs at the end of this 16-bit transmis-
sion to start the next frame. If both this bit and the Mark/Flag Idle bit are set to ‘1’, all ‘1’s
are transmitted after the transmit underrun. This bit should be set after the first byte of
data is sent to the SCC and reset immediately after the last byte of data so that the frame
will be terminated properly with CRC and a flag. This bit is ignored in Loop mode, but the
programmed value is active upon exiting Loop mode. This bit is reset by a channel or
hardware reset.
Bit 1: Loop Mode
In SDLC mode, the initial set condition of this bit forces the SCC to connect TxD to TxD
and to begin searching the incoming data stream so that it can go on-loop. All bits perti-
nent to SDLC mode operation in other registers must be set before this mode is selected.
The transmitter and receiver should not be enabled until after this mode has been se-
lected. As soon as the Go Active On Poll bit is set and an EOP is received, the SCC goes
on-loop. If this bit is reset after the SCC is on-loop, the SCC waits for the next EOP to go
off-loop.
In synchronous modes, the SCC uses this bit, along with the Go Active On Poll bit, to
synchronize the transmitter to the receiver. The receiver should not be enabled until after
this mode is selected. The TxD pin is held marking when this mode is selected unless a
break condition is programmed. The receiver waits for a sync character to be received
and then enables the transmitter on a character boundary. The break condition, if pro-
grammed, is removed. This mode works properly with sync characters of 6, 8, or 16 bits.
This bit is ignored in Asynchronous mode and is reset by a channel or hardware reset.
Bit 0: 6 Bit/ 8 Bit Sync
This bit is used to select a special case of synchronous modes. If this bit is set to ‘1’ in
Monosync mode, the receiver and transmitter sync characters are six bits long instead of
the usual eight. If this bit is set to ‘1’ in Bisync mode, the received sync will be 12 bits and
the transmitter sync character will remain 16 bits long. This bit is ignored in SDLC and
Asynchronous modes but still has effect in the special external sync modes. This bit is
reset by a channel or hardware reset.
6.2.12
Write Register 11 (Clock Mode Control)
WR11 is the Clock Mode Control register. The bits in this register control the sources of
both the receive and transmit clocks, the type of signal on the Sync and RTxC pins, and
the direction of the TRxC pin. Bit positions for WR11 are shown in Figure 6–13.
6–23