MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 99

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

7.6.1.2 SWI Instruction
7.6.2 Interrupt Status Registers
MC68HC908JL8
MOTOROLA
NOTES:
1. The I bit in the condition code register is a global mask for all interrupts sources except the SWI instruction.
Priority
Highest
Lowest
NOTE:
Reset
SWI Instruction
IRQ Pin
Timer 1 Channel 0 Interrupt
Timer 1 Channel 1 Interrupt
Timer 1 Overflow Interrupt
Timer 2 Channel 0 Interrupt
Timer 2 Channel 1 Interrupt
Timer 2 Overflow Interrupt
SCI Error
SCI Receive
SCI Transmit
Keyboard Interrupt
ADC Conversion Complete Interrupt
—
Rev. 2.0
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
The flags in the interrupt status registers identify maskable interrupt
sources.
status register flags that they set. The interrupt status registers can be
useful for debugging.
Source
Freescale Semiconductor, Inc.
For More Information On This Product,
Table 7-3
Table 7-3. Interrupt Sources
System Integration Module (SIM)
Go to: www.freescale.com
summarizes the interrupt sources and the interrupt
COCO
SCRF
SCTE
KEYF
CH0F
CH1F
CH0F
CH1F
IRQF
IDLE
Flag
TOF
TOF
OR
NF
FE
PE
TC
—
—
Mask
IMASKK
IMASK
SCRIE
CH0IE
CH1IE
CH0IE
CH1IE
SCTIE
ORIE
TOIE
TOIE
NEIE
PEIE
TCIE
AIEN
FEIE
ILIE
—
—
1(1)
System Integration Module (SIM)
INT Flag
IF11
IF12
IF13
IF14
IF15
IF1
IF3
IF4
IF5
IF6
IF7
IF8
—
—
Vector Address
Exception Control
$FFEC–$FFED
$FFDE–$FFDF
$FFFC–$FFFD
$FFEE–$FFEF
$FFFE–$FFFF
$FFFA–$FFFB
$FFE6–$FFE7
$FFE4–$FFE5
$FFE2–$FFE3
$FFE0–$FFE1
$FFF6–$FFF7
$FFF4–$FFF5
$FFF2–$FFF3
$FFF0–$FFF1
Technical Data
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