MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 87

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MC68HC908JL8

Manufacturer Part Number
MC68HC908JL8
Description
Motorola reserves the right to make changes without further notice to any products herein
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet

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MC68HC908JL8
MOTOROLA
Signal Name
PIN LOGIC
OSCOUT
PORRST
RESET
IRST
INTERNAL
ICLK
R/W
IDB
IAB
PULL-UP
Rev. 2.0
VDD
Internal oscillator clock
The XTAL or RC frequency divided by two. This signal is again divided by two in the
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
SIM to generate the internal bus clocks. (Bus clock = OSCOUT ÷ 2)
SIM RESET STATUS REGISTER
Freescale Semiconductor, Inc.
RESET PIN CONTROL
For More Information On This Product,
POR CONTROL
Table 7-1. Signal Name Conventions
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
Figure 7-1. SIM Block Diagram
INTERRUPT CONTROL
CLOCK
System Integration Module (SIM)
Go to: www.freescale.com
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
CONTROL
MASTER
RESET
Description
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
ICLK (FROM OSCILLATOR)
OSCOUT (FROM OSCILLATOR)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
INTERRUPT SOURCES
CPU INTERFACE
System Integration Module (SIM)
Technical Data
Introduction
87

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