MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 253

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

16.5 COP Control Register
16.6 Interrupts
16.7 Monitor Mode
16.8 Low-Power Modes
16.8.1 Wait Mode
MC68HC908JL8
MOTOROLA
—
Rev. 2.0
Address:
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
The COP does not generate CPU interrupt requests.
The COP is disabled in monitor mode when V
pin or on the RST pin.
The WAIT and STOP instructions put the MCU in low-power
consumption standby modes.
The COP continues to operate during wait mode. To prevent a COP
reset during wait mode, periodically clear the COP counter in a CPU
interrupt routine.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
For More Information On This Product,
$FFFF
Computer Operating Properly (COP)
Bit 7
Figure 16-3. COP Control Register (COPCTL)
Go to: www.freescale.com
6
5
Low byte of reset vector
Unaffected by reset
Clear COP counter
4
Computer Operating Properly (COP)
3
TST
is present on the IRQ
2
COP Control Register
1
Technical Data
Bit 0
253