MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 221

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

13.3.2 Data Direction Register A (DDRA)
MC68HC908JL8
MOTOROLA
NOTE:
NOTE:
—
Rev. 2.0
Address:
Data direction register A determines whether each port A pin is an input
or an output. Writing a logic 1 to a DDRA bit enables the output buffer for
the corresponding port A pin; a logic 0 disables the output buffer.
For those devices packaged in a 28-pin package, PTA7 is not
connected. DDRA7 should be set to a 1 to configure PTA7 as an output.
For those devices packaged in a 20-pin package, PTA0–PTA5 and
PTA7 are not connected. DDRA0–DDRA5 and DDRA7 should be set to
a 1 to configure PTA0–PTA5 and PTA7 as outputs.
DDRA[7:0] — Data Direction Register A Bits
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 13-4
Reset:
Read:
Write:
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A pins as inputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
DDRA7
$0004
Bit 7
0
Figure 13-3. Data Direction Register A (DDRA)
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shows the port A I/O logic.
Input/Output (I/O) Ports
DDRA6
6
0
DDRA5
5
0
DDRA4
4
0
DDRA3
3
0
DDRA2
2
0
Input/Output (I/O) Ports
DDRA1
1
0
Technical Data
DDRA0
Bit 0
Port A
0
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