MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 228

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

Input/Output (I/O) Ports
13.5.2 Data Direction Register D (DDRD)
Technical Data
228
NOTE:
Address:
ADC11–ADC8 — ADC channels 11 to 8
T1CH1, T1CH0 — Timer 1 Channel I/Os
TxD, RxD — SCI Data I/O Pins
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
For those devices packaged in a 20-pin package, PTD0–PTD1 and are
not connected. DDRD0–DDRD1 should be set to a 1 to configure
PTD0–PTD1 as outputs.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
ADC[11:8] are pins used for the input channels to the analog-to-digital
converter module. The channel select bits, ADCH[4:0], in the ADC
status and control register define which port pin will be used as an
ADC input and overrides any control from the port I/O logic. See
Section 12. Analog-to-Digital Converter
The T1CH1 and T1CH0 pins are the TIM1 input capture/output
compare pins. The edge/level select bits, ELSxB:ELSxA, determine
whether the PTD4/T1CH0 and PTD5/T1CH1 pins are timer channel
I/O pins or general-purpose I/O pins. See
Interface Module
The TxD and RxD pins are the transmit data output and receive data
input for the SCI module. The enable SCI bit, ENSCI, in the SCI
control register 1 enables the PTD6/TxD and PTD7/RxD pins as SCI
TxD and RxD pins and overrides any control from the port I/O logic.
See
For More Information On This Product,
Section 11. Serial Communications Interface
DDRD7
$0007
Bit 7
Figure 13-11. Data Direction Register D (DDRD)
0
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Input/Output (I/O) Ports
DDRD6
6
0
(TIM).
DDRD5
5
0
DDRD4
4
0
DDRD3
3
0
Section 10. Timer
(ADC).
DDRD2
MC68HC908JL8
2
0
(SCI).
DDRD1
1
0
MOTOROLA
—
Rev. 2.0
DDRD0
Bit 0
0