MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 121

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908JL8
MOTOROLA
—
Rev. 2.0
If V
(Table 9-1
clock input to OSC1. If PTB3 is high with V
monitor mode entry
divide-by-four of the clock input to OSC1. Holding the PTB3 pin low
when entering monitor mode causes a bypass of a divide-by-two stage
at the oscillator only if V
frequency is equal to the 2OSCOUT frequency, and OSC1 input directly
generates internal bus clocks. In this case, the OSC1 signal must have
a 50% duty cycle at maximum bus frequency.
Entering monitor mode with V
as V
Integration Module (SIM)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF)
applied voltage is V
including the PTB3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
Figure
the reset vector is blank and IRQ = V
9.8304MHz is required for a baud rate of 9600.
Freescale Semiconductor, Inc.
TST
TST
For More Information On This Product,
is applied to IRQ and PTB3 is low upon monitor mode entry
9-2. shows a simplified diagram of the monitor mode entry when
is applied to either IRQ or RST. (See
condition set 1), the bus frequency is a divide-by-two of the
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Monitor ROM (MON)
DD
(Table 9-1
), then all port B pin requirements and conditions,
TST
for more information on modes of operation.)
is applied to IRQ. In this event, the OSCOUT
TST
condition set 2), the bus frequency is a
(Table 9-1
on IRQ, the COP is disabled as long
DD
. An OSC1 frequency of
TST
condition set 3, where
Section 7. System
applied to IRQ upon
Functional Description
Monitor ROM (MON)
Technical Data
121