MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 61

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

5.4 Configuration Register 1 (CONFIG1)
MC68HC908JL8
MOTOROLA
NOTE:
—
Rev. 2.0
Configuration and Mask Option Registers (CONFIG & MOR)
Address:
COPRS — COP Rate Select Bit
LVID — Low Voltage Inhibit Disable Bit
SSREC — Short Stop Recovery Bit
Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal, do not set the SSREC bit.
STOP — STOP Instruction Enable Bit
Reset:
Read:
Write:
COPRS selects the COP time-out period. Reset clears COPRS.
(See
LVID disables the LVI module. Reset clears LVID.
(See
SSREC enables the CPU to exit stop mode with a delay of
32 ICLK cycles instead of a 4096 ICLK cycle delay.
STOP enables the STOP instruction.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = COP timeout period is (2
0 = COP timeout period is (2
1 = Low voltage inhibit disabled
0 = Low voltage inhibit enabled
1 = Stop mode recovery after 32 ICLK cycles
0 = Stop mode recovery after 4096 ICLK cycles
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPRS
$001F
Section 16. Computer Operating Properly
Section 17. Low Voltage Inhibit
Bit 7
Figure 5-2. Configuration Register 1 (CONFIG1)
R
0
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= Reserved
R
6
0
Configuration and Mask Option Registers (CONFIG & MOR)
R
5
0
LVID
13
18
4
0
– 2
– 2
4
4
) ICLK cycles
) ICLK cycles
Configuration Register 1 (CONFIG1)
(LVI).)
R
3
0
SSREC
2
0
(COP).)
STOP
1
0
Technical Data
COPD
Bit 0
0
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