MC68HC908JL8 MOTOROLA [Motorola, Inc], MC68HC908JL8 Datasheet - Page 123

• Manufacturer Part Number: MC68HC908JL8
• Description: Motorola reserves the right to make changes without further notice to any products herein
• Manufacturer: MOTOROLA [Motorola, Inc]

9.4.2 Baud Rate
MC68HC908JL8
MOTOROLA
—
Rev. 2.0
Table 9-2
and monitor mode.
When the host computer has completed downloading code into the MCU
RAM, the host then sends a RUN command, which executes an RTI,
which sends control to the address on the stack pointer.
The communication baud rate is dependant on oscillator frequency. The
state of PTB3 also affects baud rate if entry to monitor mode is by
IRQ = V
pin is at logic zero upon entry into monitor mode, the divide by ratio is
512.
Monitor
Modes
User
Notes:
1. If the high voltage (V
Blank reset vector,
Freescale Semiconductor, Inc.
Monitor Mode
its COP enable output. The COP is a mask option enabled or disabled by the COPD bit
in the configuration register.
For More Information On This Product,
IRQ = V
IRQ = V
Entry By:
TST
Disabled
is a summary of the vector differences between user mode
Enabled
. When PTB3 is high, the divide by ratio is 1024. If the PTB3
TST
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DD
Table 9-2. Monitor Mode Vector Differences
COP
Table 9-3. Monitor Baud Rate Selection
Monitor ROM (MON)
(1)
TST
Vector
$FFFE
$FEFE
Reset
) is removed from the IRQ pin or the RST pin, the SIM asserts
High
OSC1 Clock
4.9152 MHz
9.8304 MHz
4.9152 MHz
9.8304 MHz
4.9152 MHz
Frequency
Vector
$FFFF
$FEFF
Reset
Low
Functions
Vector
$FFFC
$FEFC
Break
High
PTB3
X
X
0
1
1
Vector
$FEFD
$FFFD
Break
Low
Functional Description
Monitor ROM (MON)
Baud Rate
9600 bps
9600 bps
4800 bps
9600 bps
4800 bps
Vector
$FFFC
$FEFC
High
SWI
Technical Data
$FEFD
Vector
$FFFD
Low
SWI
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