PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 73

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 4- Motor Enable 0
Bit 5 - Motor Enable 1
Bit 6 - Motor Enable 2
Bit 7 - Motor Enable 3
5.3.4
The TDR register is a read/write register that acts as the
Floppy Disk Controller’s (FDC) media and drive type regis-
ter.
The TDR functions differently, depending on the mode set
by bit 6 the SuperI/O FDC Configuration register at index
F0h. See “Bit 6 - TDR Register Mode” on page 37.
AT Compatible
TDR Mode
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See Table 5-2.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 0.
0 - The motor signal for drive 0 is not active.
1 - The motor signal for drive 0 is active.
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 0, depending on
the remaining bits of this register. See Table 5-2.
If two drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 0), this bit controls
the motor output signal for drive 1.
0 - The motor signal for drive 1 is not active.
1 - The motor signal for drive 1 is active.
If drives 2 and 0 are exchanged (see logical drive ex-
change bits 3,2 of TDR on page 74), or if four drives are
supported (bit 7 of the SuperI/O FDC Configuration reg-
ister at index F0h is 1), this bit controls the motor output
signal for drive 2. See Table 5-2.
0 - The motor signal for drive 2 is not active.
1 - The motor signal for drive 2 is active.
If four drives are supported (bit 7 of the SuperI/O FDC
Configuration register at index F0h is 1), this bit may
control the motor output signal for drive 3, depending on
the remaining bits of this register. See Table 5-2.
0 - The motor signal for drive 3 is not active.
1 - The motor signal for drive 3 is active.
Enhanced
Tape Drive Register (TDR), Offset 03h
FDC Configuration
Bit 6 of SuperI/O
TABLE 5-4. TDR Bit Utilization and Reset Values in Different Drive Modes
Register
0
1
The Digital Floppy Disk Controller (FDC) (Logical Device 3)
Not Reset Not Reset
Density
Extra
7
Not used. Floated in TRI-STATE during read operations.
Density
High
6
73
Drive ID1 Drive ID0
AT Compatible TDR Mode
In this mode, the TDR assigns a drive number to the tape
drive support mode of the data separator. All other logical
drives can be assigned as floppy drive support. Bits 7-2 are
in TRI-STATE during read operations.
Enhanced TDR Mode
In this mode, all the bits of the TDR define operations with
PS/2 floppy disk drives.
FIGURE 5-9. TDR Register Bitmap, Enhanced TDR
FIGURE 5-8. TDR Register Bitmap, AT Compatible
7
7
5
1
Extra Density
6
6
High Density
5
5
Bits of TDR
Drive ID1 Information
1
1
4
4
4
1
Not Used
TRI-STATE During Read Operations
AT Compatible TDR Mode
Drive ID0 Information
3
3
Enhanced TDR Mode
2
2
TDR Mode
Logical Drive Exchange
0
0
1
1
Logical Drive
Mode
3
0
Exchange
0
0
0
0
Tape Drive Select 1,0
Tape Drive Select 1,0
Reset
Required
Reset
Required
2
0
Register (TDR)
Register (TDR)
Drive Select
Tape Drive
Tape Drive
Offset 03h
Offset 03h
0
www.national.com
1
0
0
0
0