PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 22

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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WGATE
WP
WR
WRITE
X1
X1C
X2C
XD7,6,
XD1,0
XD5-2
XDCS
XDRD
ZWS
Signal/Pin
Name
93
98
34
112
50
62
63
78, 77
72, 71
76-73
69
70
31
Number
Pin
Parallel Port
ISA-Bus
ISA-Bus
Module
X-Bus
X-Bus
X-Bus
X-Bus
Clock
FDC
FDC
RTC
RTC
Signal/Pin Connection and Description
Group 16
Group 23
Group 10
Group 22
Group #
Group 1
Group 1
Group 6
Group 9
Group 7
Group 1
I/O and
Output
Output
Output
Output
Input
Input
Input
Input
Input
Input
I/O
I/O
Write Gate (FDC) – This output signal enables the write circuitry of
the selected disk drive. WGATE is designed to prevent glitches
during power up and power down. This prevents writing to the disk
when power is cycled.
Write Protected – This input signal indicates that the disk in the
selected drive is write protected.
I/O Write – WR is an active low input signal that indicates a write
operation from the microprocessor to the controller.
Write Strobe – In EPP mode, this active low signal is a write strobe.
This signal is multiplexed with STB. See Table 6-12 on page 134 for
more information.
Clock In – A TTL or CMOS compatible 24 MHz or 48 MHz clock.
See Chapter 11.
Crystal 1 Slow – Input signal to the internal Real-Time Clock (RTC)
crystal oscillator amplifier.
Crystal 2 Slow – Output signal from the internal Real-Time Clock
(RTC) crystal oscillator amplifier.
X-Bus Data – These bidirectional signals hold the data in the X Data
Buffer (XDB).
XD7 is multiplexed with IRSL1 and ID1.
XD6 is multiplexed with IRSL2, SELCS and GPIO21.
XD5-2 are multiplexed with GPIO27-24, respectively.
XD1,0 are multiplexed with CS2,1 respectively.
See Table 1-2 on page 23.
X-Bus Data Buffer (XDB) Chip Select – This signal enables and
disables the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with RING. See Table 1-2 on page 23.
X-Bus Data Buffer (XDB) Read Command – This signal controls
the direction of the bidirectional XD7-0 data buffer signals.
This signal is multiplexed with ID3. See Table 1-2 on page 23.
Zero Wait State – When this open-drain output signal is activated
(driven low), it indicates that the access time can be shortened, i.e.,
zero wait states.
ZWS is never activated (driven low) on access to SuperI/O chip
configuration registers (including during the Isolation state) or on
access to the parallel port in SPP or EPP 1.9 mode.
ZWS is always activated (driven low) on access to the parallel port in
ECP mode.
Assertion of ZWS on access to a parallel port in EPP 1.7 mode is
controlled by bit 3 of the Control2 register (at second level offset 02h)
of the parallel port (accessed by the Index and Data registers at
base+403h and base+404h). See page 127.
Bit 0 of the SuperI/O Configuration 1 register (at index 21h) controls
assertion of ZWS on access to any other addresses of the part. See
page 35.
22
Function