PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 53

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

AF bit of CRC
PF bit of CRC
UIP bit of CRA
UF bit of CRC
TABLE 4-2. Periodic Interrupt Rate Encoding
3 2 1 0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
RS3-0
FIGURE 4-5. Interrupt/Status Timing
A-B
D-C
C-E
UIP
UF
PF
AF
Flags (and IRQ) are reset at the conclusion of Control Register C (CRC) read or by reset.
Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2)
Update In Progress (UIP) bit high before update occurs = 244 sec
Periodic interrupt to update = Period (periodic int) / 2 + 244 sec
Update to Alarm Interrupt = 30.5 s
Update In Progress status bit
Update-Ended Interrupt Flag (Update-Ended Interrupt if enabled)
Periodic Flag (Periodic Interrupt if enabled)
Alarm Flag (Alarm Interrupt if enabled)
Periodic Interrupt Rate
1.953125
3.90625
122.070
244.141
488.281
976.562
3.90625
7.8125
7.8125
15.625
D
31.25
none
62.5
125
250
500
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
msec
sec
sec
sec
sec
A
53
TABLE 4-3. Divider Chain Control and Bank Selection
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
6
DV2-0
a. The oscillator stops in this case only in the
5 4
event of a power failure.
C
B
Undefined
Selected
Bank 0
Bank 0
Bank 0
Bank 1
Bank 2
Bank 0
Bank 0
Bank
E
Divider Chain Reset
Divider Chain Reset
Oscillator Disabled
Oscillator Disabled
Normal Operation
Normal Operation
Normal Operation
Configuration
Test
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a
a