PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 99

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Result Phase
See Table 5-18 for the state of the result bytes when the
command terminates normally.
5.7.12 The READ ID Command
The READ ID command finds the next available address
field and returns the ID bytes (track number, head number,
sector number, bytes-per-sector code) to the microproces-
sor in the result phase.
The controller reads the first ID Field header bytes it can
find and reports these bytes to the system in the result
bytes.
Command Phase
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see Table 5-25 on
page 106) for the selected drive. During this time, the drive
motor must be turned on by enabling the appropriate drive
and motor select disk interface output signals via the bits of
the Digital Output Register (DOR). See “Digital Output Reg-
ister (DOR), Offset 02h” on page 71.
Control
X
7
7
0
TABLE 5-19. SK Effect on READ DELETED DATA
Skip
(SK)
0
0
1
1
MFM
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
X
6
6
Deleted
Deleted
Normal
Normal
Data
Type
X
5
Bytes-Per-Sector Code
5
0
Sector
Read?
Sector Number
Track Number
Head Number
Command
Y
Y
N
Y
X
4
4
0
Mark Bit 6
Control
of ST2
X
3
3
1
1
0
1
0
HD
2
2
0
Sector Skipped
Sectors Read
Termination
Termination
DS1
No More
Normal
Normal
Result
1
1
1
DS0
0
0
0
99
First Command Phase Byte, Opcode
Second Command Phase Byte
Execution Phase
There is no data transfer during the execution phase of this
command. An interrupt is generated when the execution
phase is completed.
The READ ID command does not perform an implied seek.
After waiting the Delay Before Processing time, the control-
ler starts the data separator and waits for the data separator
to find the address field of the next sector. If an error condi-
tion occurs, the Interrupt Code (IC) bits in ST0 are set to ab-
normal termination (01), and the controller enters the result
phase.
Possible errors are:
Result Phase
•
•
7
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 90.
See “Second Command Phase Byte” on page 90 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
The microprocessor aborted the command by writing to
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
Two pulses of the INDEX signal were detected since the
search began, and no Address Mark (AM) was found.
When the Address Mark (AM) is not found, the Missing
Address Mark bit (bit 0) is set in ST1. Section 5.5.2 on
page 81 describes the bits of ST1.
6
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
5
Bytes-Per-Sector Code
Sector Number
Track Number
Head Number
4
3
2
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