PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 172

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

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9.0 Power Management
9.1 POWER MANAGEMENT OPTIONS
The power management logical device provides configura-
tion options and control of the WATCHDOG feature.
9.1.1
Registers in this logical device enable activation of other
logical devices, and set I/O characteristics for certain pins.
(See Section 9.2)
9.1.2
The WATCHDOG feature lets you implement power saving
strategies that power down the entire system if it is unused
for a defined period of time. This feature is especially attrac-
tive for battery-powered systems.
The WATCHDOG function generates the WDO output sig-
nal, which the system may use to implement power-down
activities.
The WATCHDOG function is activated by setting the
WATCHDOG Time-Out (WDTO) register to a value from 1
through 255 minutes. This defines a maximum countdown
period. The WATCHDOG timer starts with this value and
counts down to 0 unless a trigger event restarts the count.
The WATCHDOG Configuration register (WDCF) specifies
the trigger events that cause reloading of the WATCHDOG
time-out value into the timer and restart the countdown. See
“WATCHDOG Configuration Register (WDCF), Index 06h”
on page 175.
If the timer reaches zero, it is disabled, the WDO signal be-
comes active (low) and the host system can use WDO to
trigger power down.You can monitor the state of the WDO
signal at any time by reading bit 1 of the WATCHDOG Sta-
tus (WDST) register.
9.2 THE POWER MANAGEMENT REGISTERS
The power management registers are accessed via the
Power Management Index and Data registers, which are lo-
cated at base address and base address + 01h, respective-
ly. The base address is indicated by the Base Address
registers at indexes 60h and 61h of logical device 8, respec-
tively. See Table 2-20 on page 34.
Table 9-1 lists the power management registers.
(Logical Device 8)
Configuration Options
The WATCHDOG Feature
Power Management (Logical Device 8)
172
9.2.1
This read/write register is reset by hardware to 00h. It points
to one of the power management registers. Bits 7 through 3
are read only and return 00000 when read.
The data in the indicated register is accessed via the Power
Management Data register at the base address + 01h.
Base+0
Base+1
Index Symbol
0
0
00h
01h
02h
03h
04h
05h
06h
07h
7
FIGURE 9-1. Power Management Index Register
TABLE 9-1. The Power Management Registers
0
0
6
Power Management Index Register,
Base Address + 00h
WDTO
WDCF WATCHDOG Configuration Register R/W
WDST
PMC1
PMC2
PMC3
FER1
FER2
0
0
5
0
0
4
Read Only
Power Management Index Register R/W
Power Management Data Register R/W
0
0
3
WATCHDOG Time-Out Register
Power Management Control 1
Power Management Control 2
Power Management Control 3
WATCHDOG Status Register
Function Enable Register 1
Function Enable Register 2
0
2
0
1
Bitmap
Description
0
Index of a Power
Management Register
0
Reset
Required
Power Management
Index Register,
Base Address
+ 00h
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W