PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 117

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

6.3.9
This is the fourth EPP data register. It is only accessed to
transfer bits 31 through 24 of a 32-bit read or write to EPP
Data Register 0 (DATA0).
6.3.10 EPP Mode Transfer Operations
The EPP transfer operations are address read or write, and
data read or write. An EPP transfer is composed of a sys-
tem read or write cycle from or to an EPP register, and an
EPP read or write cycle from a peripheral device to an EPP
register or from an EPP register to a peripheral device.
EPP 1.7 Address Write
The following procedure selects a peripheral device or reg-
ister as illustrated in Figure 6-12.
1. The system writes a byte to the EPP Address register.
2. The EPP pulls ASTRB low to indicate that data was
3. If WAIT was low during the system write cycle,
4. When IOCHRDY becomes high, it causes WR to be-
5. When WR becomes high, it causes the EPP to pull first
0
7
WR becomes low to latch D7-0 into the EPP Address
register. The latch drives the EPP Address register onto
PD7-0 and the EPP pulls WRITE low.
sent.
IOCHRDY becomes low. When WAIT becomes high,
the EPP pulls IOCHRDY high.
come high. If WAIT is high during the system write cycle,
then the EPP does not pull IOCHRDY to low.
ASTRB and then WRITE to high. The EPP can change
PD7-0 only when WRITE and ASTRB are both high.
0
D31
6
FIGURE 6-11. EPP DATA3 Register Bitmap
EPP Data Register 3 (DATA3), Offset 07h
D30
0
5
D29
0
4
D28
0
3
D27
0
2
EPP Device
Read or Write Data
D26
0
1
D25
0
0
Reset
Required
D24
EPP Data Register 3
Parallel Port (Logical Device 4)
Offset 07h
(DATA3)
117
EPP 1.7 Address Read
The following procedure reads from the EPP Address reg-
ister as shown in Figure 6-13.
1. The system reads a byte from the EPP Address register.
2. The EPP pulls ASTRB low to signal the peripheral to
3. If WAIT is low during the system read cycle. Then the
4. When IOCHRDY becomes high, it causes RD to be-
5. When RD becomes high, it causes the EPP to pull
IOCHRDY
IOCHRDY
RD goes low to gate PD7-0 into D7-0.
start sending data.
EPP pulls IOCHRDY low. When WAIT becomes high,
the EPP stops pulling IOCHRDY to low.
come high. If WAIT is high during the system read cycle
then the EPP does not pull IOCHRDY to low.
ASTRB high. The EPP can change PD7-0 only when
ASTRB is high. After ASTRB becomes high, the EPP
puts D7-0 in TRI-STATE.
ASTRB
WRITE
ASTRB
WRITE
PD7-0
WAIT
PD7-0
ZWS
WAIT
D7-0
ZWS
D7-0
WR
RD
FIGURE 6-12. EPP 1.7 Address Write
FIGURE 6-13. EPP 1.7 Address Read
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