PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 93

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bits 3,2 - Low-Power Mode (LOW PWR)
Bit 5 - Implied Seek (IPS)
Bit 6 - Index Address Format (IAF)
Bit 7 - Motor Timer Values (TMR)
These bits determine whether or not the FDC powers
down and, if it does, they specific how long it will take.
These bits disable power down, i.e., are cleared to 0, af-
ter a software reset.
00 - Disables power down. (Default)
01 - Automatic power down.
10 - Manual power down.
11 - Not used.
This bit determines whether the Implied Seek (IPS) bit
in a command phase byte of a read, write, scan, or verify
command is ignored or READ.
A software reset clears this bit to its default value of 0.
0 - The IPS bit in the command byte of a read, write,
1 - The IPS bit in the command byte of a read, write,
This bit determines whether the controller formats
tracks with or without an index address field.
A software reset clears this bit to its default value of 0.
0 - The controller formats tracks with an index address
1 - The controller formats tracks without an index ad-
This bit determines which group of values to use to cal-
culate the Delay Before Processing and Delay After Pro-
cessing times. The value of each is programmed using
the SPECIFY command, which is described on page
105 and in Tables 5-24 and 5-25.
A software reset clears this bit to its default value of 0.
0 - Use the TMR = 0 group of values. (Default)
1 - Use the TMR = 1 group of values.
At a 500 Kbps data transfer rate, the FDC goes into
low-power mode 512 msec after it becomes idle.
At a 250 Kbps data transfer rate, the FDC goes into
low-power mode 1 second after it becomes idle.
The FDC powers down mode immediately.
scan, or verify is ignored. (Default)
Implied seeks can still be enabled by the Enable
Implied Seeks (EIS) bit (bit 6 of the third command
phase byte) in the CONFIGURE command.
scan, or verify is read.
If it is set to 1, the controller performs seek and
sense interrupt operations before executing the
command.
field. (IBM and Toshiba Perpendicular format).
dress field. (ISO format).
93
Third Command Phase Byte
Bit 4 - RECALIBRATE Step Pulses (R255)
Bit 5 - Burst Mode Disable (BST)
Bit 6 - FIFO Read Disable (FRD)
Bit 7 - FIFO Write Enable or Disable (FWR)
This bit determines the maximum number of RECALI-
BRATE step pulses the controller issues before termi-
nating with an error, depending on the value of the
Extended Track Range (ETR) bit, i.e., bit 0 of the sec-
ond command phase byte in the MODE command.
A software reset clears this bit to its default value of 0.
0 - If ETR (bit 0) = 0, the controller issues a maximum
1 - If ETR (bit 0) = 0, the controller issues a maximum
This bit enables or disables burst mode, if the FIFO is
enabled (bit 5 in the CONFIGURE command is 0). If the
FIFO is not enabled in the CONFIGURE command, then
the value of this bit is ignored.
A software reset enables burst mode, i.e., clears this bit
to its default value of 0, if the LOCK bit (bit 7 of the op-
code of the LOCK command) is 0. If it is 1, BST retains
its value after a software reset.
0 - Burst mode enabled for FIFO execution phase data
1 - Burst mode disabled.
This bit enables or disables the FIFO for microprocessor
read transfers from the controller, if the FIFO is enabled
(bit 5 in the CONFIGURE command is 0). If the FIFO is
not enabled in the CONFIGURE command, then the val-
ue of this bit is ignored.
A software reset enables the FIFO for reads, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FRD
retains its value after a software reset.
0 - Enable FIFO. Execution phase of microprocessor
1 - Disable FIFO. All read data transfers take place
This bit enables or disables write transfers to the con-
troller, if the FIFO is enabled (bit 5 in the CONFIGURE
command is 0). If the FIFO is not enabled in the CON-
FIGURE command, then the value of this bit is ignored.
A software reset enables the FIFO for writes, i.e., clears
this bit to its default value of 0, if the LOCK bit (bit 7 of
the opcode of the LOCK command) is 0. If it is 1, FWR
retains its value after a software reset.
0 - Enable FIFO. Execution phase microprocessor
1 - Disable FIFO. All write data transfers take place
of 85 recalibration step pulses.
If ETR (bit 0) = 1, the controller issues a maximum
of 3925 recalibration step pulses. (Default)
of 255 recalibration step pulses.
If ETR (bit 0) = 1, the controller issues a maximum
of 4095 recalibration step pulses.
transfers. (Default)
The FDC issues one DRQ or IRQ6 pulse for each
byte to be transferred while the FIFO is enabled.
read transfers use the internal FIFO. (Default)
without the FIFO.
write transfers use the internal FIFO. (Default)
without the FIFO.
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