PC87307VUL National Semiconductor, PC87307VUL Datasheet - Page 151

• Manufacturer Part Number: PC87307VUL
• Description: PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O
• Manufacturer: National Semiconductor

Bit 2 - Set End of Transmission (S_EOT)
Bit 3 - Reserved
Bit 4 - Reception Watchdog (RXWDG)
Bit 5 - Receiver Active (RXACT)
Bit 6 - Infrared Transmitter Underrun (TXUR)
Bit 7 - Reserved
Bank 1 – The LEGACY Baud Generator DIVISOR
This register bank contains two baud generator divisor
ports, and a bank select register.
The Legacy Baud-rate Generator Divisor (LBGD) port pro-
vides an alternate path to the Baud Divisor Generator reg-
ister. This bank is implemented to maintain compatibility
with 16550 standard and to support existing legacy soft-
ware packages. In case of using legacy software, the ad-
dresses 0 and 1 are shared with the data ports RXD/TXD
(see page 141). The selection between them is controlled
by the value of the BKSE bit (LCR bit 7 page 145).
In Consumer-IR mode this is the Set End of Transmis-
sion bit. When a 1 is written into this bit position before
writing the last character into the TX_FIFO, data trans-
mission is gracefully completed.
In this mode, if the CPU simply stops writing data into
the TX_FIFO at the end of the data stream, a transmitter
underrun is generated and the transmitter stops. In this
case this is not an error, but the software must clear the
underrun before the next transmission can occur. This
bit is automatically cleared by hardware when a charac-
ter is written to the TX_FIFO.
Read/Write 0.
In Consumer-IR mode, this is the Reception Watchdog
(RXWDG) bit. It is set to 1 each time a pulse or pulse-
train (modulated pulse) is detected by the receiver. It
can be used by the software to detect a receiver idle
condition. It is cleared upon read.
In Consumer-IR Mode this is the Receiver Active (RX-
ACT) bit. It is set to 1 when an infrared pulse or pulse-
train is received. If a 1 is written into this bit position, the
bit is cleared and the receiver is deactivated. When this
bit is set, the receiver samples the infrared input contin-
uously at the programmed baud rate and transfers the
data to the RX_FIFO. See “Consumer-IR Reception” on
page 138.
In the Consumer-IR mode, this is the Transmitter Un-
derrun flag. This bit is set to 1 when a transmitter under-
run occurs. It is always cleared when a mode other than
Consumer-IR is selected. This bit must be cleared, by
writing 1 into it, to re-enable transmission.
Read/Write 0.
PORTS
UART1 and UART2 (with IR) (Logical Devices 5 and 6)
151
In addition, a fallback mechanism maintains this compatibil-
ity by forcing the UART to revert to 16550 mode if 16550
software addresses the module after a different mode was
set. Since setting the baud divisor values is a necessary ini-
tialization of the 16550, setting the divisor values in bank 1
forces the UART to enter 16550 mode. (This is called fall-
back.)
To enable other modes to program their desired baud rates
without activating this fallback mechanism, the baud divisor
register in bank 2 should be used.
7.11.12 Legacy Baud Generator Divisor Ports
The programmable baud rates in the Non-Extended mode
are achieved by dividing a 24 MHz clock by a prescale value
of 13, 1.625 or 1. This prescale value is selected by the
PRESL field of EXCR2 (see page 155). This clock is subdi-
vided by the two baud generator divisor buffers, which output
a clock at 16 times the desired baud rate (this clock is the
BAUDOUT clock). This clock is used by I/O circuitry, and af-
ter a last division by 16 produces the output baud rate.
Divisor values between 1 and 2
forbidden). The baud generator divisor must be loaded dur-
ing initialization to ensure proper operation of the baud gen-
erator. Upon loading either part of it, the baud generator
counter is immediately loaded. Table 7-14 on page 153
shows typical baud divisors. After reset the divisor register
contents are indeterminate.
Any access to the LBGD(L) or LBGD(H) ports causes a re-
set to the default Non-Extended mode, i.e., 16550 mode
(See “Automatic Fallback to A Non-Extended UART Mode”
on page 140).To access a Baud Generator Divisor when in
the Extended mode, use the port pair in bank 2 (BGD on
page 152).
Table 7-12 shows the bits which are cleared when Fallback
occurs during Extended or Non-Extended modes.
If the UART is in Non-Extended mode and the LOCK bit is
1, the content of the divisor (BGD) ports will not be affected
and no other action is taken.
When programming the baud rate, the new divisor is loaded
upon writing into LBGD(L) and LBGD(H). After reset, the
contents of these registers are indeterminate.
Divisor values between 1 and 2
forbidden.) Table 7-14 shows typical baud divisors.
04h - 07h
Offset
00h
01h
02h
03h
(LBGD(L) and LBGD(H)),
Bank 1, Offsets 00h and 01h
TABLE 7-11. Bank 1 Register Set
LBGD(H) Legacy Baud Generator Divisor
Register
LBGD(L)
Name
LCR/
BSR
Legacy Baud Generator Divisor
Reserved
Bank Select Register
Reserved
16
16
Port (High Byte)
Port (Low Byte)
-1 can be used. (Zero is
-1 can be used. (Zero is
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